1 # SPDX-License-Identifier: GPL-2.0-only OR BSD 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/display/msm 4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-20nm.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Qualcomm Display DSI 20nm PHY 7 title: Qualcomm Display DSI 20nm PHY
8 8
9 maintainers: 9 maintainers:
10 - Krishna Manikandan <quic_mkrishn@quicinc.co 10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
11 11
12 allOf: 12 allOf:
13 - $ref: dsi-phy-common.yaml# 13 - $ref: dsi-phy-common.yaml#
14 14
15 properties: 15 properties:
16 compatible: 16 compatible:
17 const: qcom,dsi-phy-20nm 17 const: qcom,dsi-phy-20nm
18 18
19 reg: 19 reg:
20 items: 20 items:
21 - description: dsi pll register set 21 - description: dsi pll register set
22 - description: dsi phy register set 22 - description: dsi phy register set
23 - description: dsi phy regulator registe 23 - description: dsi phy regulator register set
24 24
25 reg-names: 25 reg-names:
26 items: 26 items:
27 - const: dsi_pll 27 - const: dsi_pll
28 - const: dsi_phy 28 - const: dsi_phy
29 - const: dsi_phy_regulator 29 - const: dsi_phy_regulator
30 30
31 vcca-supply: 31 vcca-supply:
32 description: Phandle to vcca regulator dev 32 description: Phandle to vcca regulator device node.
33 33
34 vddio-supply: 34 vddio-supply:
35 description: Phandle to vdd-io regulator d 35 description: Phandle to vdd-io regulator device node.
36 36
37 required: 37 required:
38 - compatible 38 - compatible
39 - reg 39 - reg
40 - reg-names 40 - reg-names
41 - vddio-supply 41 - vddio-supply
42 - vcca-supply 42 - vcca-supply
43 43
44 unevaluatedProperties: false 44 unevaluatedProperties: false
45 45
46 examples: 46 examples:
47 - | 47 - |
48 #include <dt-bindings/clock/qcom,dispcc-s 48 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
49 #include <dt-bindings/clock/qcom,rpmh.h> 49 #include <dt-bindings/clock/qcom,rpmh.h>
50 50
51 dsi-phy@fd922a00 { 51 dsi-phy@fd922a00 {
52 compatible = "qcom,dsi-phy-20nm"; 52 compatible = "qcom,dsi-phy-20nm";
53 reg = <0xfd922a00 0xd4>, 53 reg = <0xfd922a00 0xd4>,
54 <0xfd922b00 0x2b0>, 54 <0xfd922b00 0x2b0>,
55 <0xfd922d80 0x7b>; 55 <0xfd922d80 0x7b>;
56 reg-names = "dsi_pll", 56 reg-names = "dsi_pll",
57 "dsi_phy", 57 "dsi_phy",
58 "dsi_phy_regulator"; 58 "dsi_phy_regulator";
59 59
60 #clock-cells = <1>; 60 #clock-cells = <1>;
61 #phy-cells = <0>; 61 #phy-cells = <0>;
62 62
63 vcca-supply = <&vcca_reg>; 63 vcca-supply = <&vcca_reg>;
64 vddio-supply = <&vddio_reg>; 64 vddio-supply = <&vddio_reg>;
65 65
66 clocks = <&dispcc DISP_CC_MDSS_AHB_CL 66 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
67 <&rpmhcc RPMH_CXO_CLK>; 67 <&rpmhcc RPMH_CXO_CLK>;
68 clock-names = "iface", "ref"; 68 clock-names = "iface", "ref";
69 }; 69 };
70 ... 70 ...
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