1 # SPDX-License-Identifier: GPL-2.0-only 1 # SPDX-License-Identifier: GPL-2.0-only
2 # Copyright 2019-2020, The Linux Foundation, A 2 # Copyright 2019-2020, The Linux Foundation, All Rights Reserved
3 %YAML 1.2 3 %YAML 1.2
4 --- 4 ---
5 5
6 $id: http://devicetree.org/schemas/display/msm 6 $id: http://devicetree.org/schemas/display/msm/gmu.yaml#
7 $schema: http://devicetree.org/meta-schemas/co 7 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 8
9 title: GMU attached to certain Adreno GPUs 9 title: GMU attached to certain Adreno GPUs
10 10
11 maintainers: 11 maintainers:
12 - Rob Clark <robdclark@gmail.com> 12 - Rob Clark <robdclark@gmail.com>
13 13
14 description: | 14 description: |
15 These bindings describe the Graphics Managem 15 These bindings describe the Graphics Management Unit (GMU) that is attached
16 to members of the Adreno A6xx GPU family. Th 16 to members of the Adreno A6xx GPU family. The GMU provides on-device power
17 management and support to improve power effi 17 management and support to improve power efficiency and reduce the load on
18 the CPU. 18 the CPU.
19 19
20 properties: 20 properties:
21 compatible: 21 compatible:
22 oneOf: 22 oneOf:
23 - items: 23 - items:
24 - pattern: '^qcom,adreno-gmu-[67][0- !! 24 - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$'
25 - const: qcom,adreno-gmu <<
26 - items: <<
27 - pattern: '^qcom,adreno-gmu-x[1-9][ <<
28 - const: qcom,adreno-gmu 25 - const: qcom,adreno-gmu
29 - const: qcom,adreno-gmu-wrapper 26 - const: qcom,adreno-gmu-wrapper
30 27
31 reg: 28 reg:
32 minItems: 1 29 minItems: 1
33 maxItems: 4 30 maxItems: 4
34 31
35 reg-names: 32 reg-names:
36 minItems: 1 33 minItems: 1
37 maxItems: 4 34 maxItems: 4
38 35
39 clocks: 36 clocks:
40 minItems: 4 37 minItems: 4
41 maxItems: 7 38 maxItems: 7
42 39
43 clock-names: 40 clock-names:
44 minItems: 4 41 minItems: 4
45 maxItems: 7 42 maxItems: 7
46 43
47 interrupts: 44 interrupts:
48 items: 45 items:
49 - description: GMU HFI interrupt 46 - description: GMU HFI interrupt
50 - description: GMU interrupt 47 - description: GMU interrupt
51 48
52 interrupt-names: 49 interrupt-names:
53 items: 50 items:
54 - const: hfi 51 - const: hfi
55 - const: gmu 52 - const: gmu
56 53
57 power-domains: 54 power-domains:
58 items: 55 items:
59 - description: CX power domain 56 - description: CX power domain
60 - description: GX power domain 57 - description: GX power domain
61 58
62 power-domain-names: 59 power-domain-names:
63 items: 60 items:
64 - const: cx 61 - const: cx
65 - const: gx 62 - const: gx
66 63
67 iommus: 64 iommus:
68 maxItems: 1 65 maxItems: 1
69 66
70 qcom,qmp: <<
71 $ref: /schemas/types.yaml#/definitions/pha <<
72 description: Reference to the AOSS side-ch <<
73 <<
74 operating-points-v2: true 67 operating-points-v2: true
75 68
76 opp-table: 69 opp-table:
77 type: object 70 type: object
78 71
79 required: 72 required:
80 - compatible 73 - compatible
81 - reg 74 - reg
82 - reg-names 75 - reg-names
83 - power-domains 76 - power-domains
84 - power-domain-names 77 - power-domain-names
85 78
86 additionalProperties: false 79 additionalProperties: false
87 80
88 allOf: 81 allOf:
89 - if: 82 - if:
90 properties: 83 properties:
91 compatible: 84 compatible:
92 contains: 85 contains:
93 enum: 86 enum:
94 - qcom,adreno-gmu-618.0 87 - qcom,adreno-gmu-618.0
95 - qcom,adreno-gmu-630.2 88 - qcom,adreno-gmu-630.2
96 then: 89 then:
97 properties: 90 properties:
98 reg: 91 reg:
99 items: 92 items:
100 - description: Core GMU registers 93 - description: Core GMU registers
101 - description: GMU PDC registers 94 - description: GMU PDC registers
102 - description: GMU PDC sequence re 95 - description: GMU PDC sequence registers
103 reg-names: 96 reg-names:
104 items: 97 items:
105 - const: gmu 98 - const: gmu
106 - const: gmu_pdc 99 - const: gmu_pdc
107 - const: gmu_pdc_seq 100 - const: gmu_pdc_seq
108 clocks: 101 clocks:
109 items: 102 items:
110 - description: GMU clock 103 - description: GMU clock
111 - description: GPU CX clock 104 - description: GPU CX clock
112 - description: GPU AXI clock 105 - description: GPU AXI clock
113 - description: GPU MEMNOC clock 106 - description: GPU MEMNOC clock
114 clock-names: 107 clock-names:
115 items: 108 items:
116 - const: gmu 109 - const: gmu
117 - const: cxo 110 - const: cxo
118 - const: axi 111 - const: axi
119 - const: memnoc 112 - const: memnoc
120 113
121 - if: 114 - if:
122 properties: 115 properties:
123 compatible: 116 compatible:
124 contains: 117 contains:
125 enum: 118 enum:
126 - qcom,adreno-gmu-635.0 119 - qcom,adreno-gmu-635.0
127 - qcom,adreno-gmu-660.1 120 - qcom,adreno-gmu-660.1
128 then: 121 then:
129 properties: 122 properties:
130 reg: 123 reg:
131 items: 124 items:
132 - description: Core GMU registers 125 - description: Core GMU registers
133 - description: Resource controller 126 - description: Resource controller registers
134 - description: GMU PDC registers 127 - description: GMU PDC registers
135 reg-names: 128 reg-names:
136 items: 129 items:
137 - const: gmu 130 - const: gmu
138 - const: rscc 131 - const: rscc
139 - const: gmu_pdc 132 - const: gmu_pdc
140 clocks: 133 clocks:
141 items: 134 items:
142 - description: GMU clock 135 - description: GMU clock
143 - description: GPU CX clock 136 - description: GPU CX clock
144 - description: GPU AXI clock 137 - description: GPU AXI clock
145 - description: GPU MEMNOC clock 138 - description: GPU MEMNOC clock
146 - description: GPU AHB clock 139 - description: GPU AHB clock
147 - description: GPU HUB CX clock 140 - description: GPU HUB CX clock
148 - description: GPU SMMU vote clock 141 - description: GPU SMMU vote clock
149 clock-names: 142 clock-names:
150 items: 143 items:
151 - const: gmu 144 - const: gmu
152 - const: cxo 145 - const: cxo
153 - const: axi 146 - const: axi
154 - const: memnoc 147 - const: memnoc
155 - const: ahb 148 - const: ahb
156 - const: hub 149 - const: hub
157 - const: smmu_vote 150 - const: smmu_vote
158 151
159 - if: 152 - if:
160 properties: 153 properties:
161 compatible: 154 compatible:
162 contains: 155 contains:
163 enum: 156 enum:
164 - qcom,adreno-gmu-640.1 157 - qcom,adreno-gmu-640.1
165 then: 158 then:
166 properties: 159 properties:
167 reg: 160 reg:
168 items: 161 items:
169 - description: Core GMU registers 162 - description: Core GMU registers
170 - description: GMU PDC registers 163 - description: GMU PDC registers
171 - description: GMU PDC sequence re 164 - description: GMU PDC sequence registers
172 reg-names: 165 reg-names:
173 items: 166 items:
174 - const: gmu 167 - const: gmu
175 - const: gmu_pdc 168 - const: gmu_pdc
176 - const: gmu_pdc_seq 169 - const: gmu_pdc_seq
177 170
178 - if: 171 - if:
179 properties: 172 properties:
180 compatible: 173 compatible:
181 contains: 174 contains:
182 enum: 175 enum:
183 - qcom,adreno-gmu-650.2 176 - qcom,adreno-gmu-650.2
184 then: 177 then:
185 properties: 178 properties:
186 reg: 179 reg:
187 items: 180 items:
188 - description: Core GMU registers 181 - description: Core GMU registers
189 - description: Resource controller 182 - description: Resource controller registers
190 - description: GMU PDC registers 183 - description: GMU PDC registers
191 - description: GMU PDC sequence re 184 - description: GMU PDC sequence registers
192 reg-names: 185 reg-names:
193 items: 186 items:
194 - const: gmu 187 - const: gmu
195 - const: rscc 188 - const: rscc
196 - const: gmu_pdc 189 - const: gmu_pdc
197 - const: gmu_pdc_seq 190 - const: gmu_pdc_seq
198 191
199 - if: 192 - if:
200 properties: 193 properties:
201 compatible: 194 compatible:
202 contains: 195 contains:
203 enum: 196 enum:
204 - qcom,adreno-gmu-640.1 197 - qcom,adreno-gmu-640.1
205 - qcom,adreno-gmu-650.2 198 - qcom,adreno-gmu-650.2
206 then: 199 then:
207 properties: 200 properties:
208 clocks: 201 clocks:
209 items: 202 items:
210 - description: GPU AHB clock 203 - description: GPU AHB clock
211 - description: GMU clock 204 - description: GMU clock
212 - description: GPU CX clock 205 - description: GPU CX clock
213 - description: GPU AXI clock 206 - description: GPU AXI clock
214 - description: GPU MEMNOC clock 207 - description: GPU MEMNOC clock
215 clock-names: 208 clock-names:
216 items: 209 items:
217 - const: ahb 210 - const: ahb
218 - const: gmu 211 - const: gmu
219 - const: cxo 212 - const: cxo
220 - const: axi 213 - const: axi
221 - const: memnoc 214 - const: memnoc
222 <<
223 - if: <<
224 properties: <<
225 compatible: <<
226 contains: <<
227 enum: <<
228 - qcom,adreno-gmu-730.1 <<
229 - qcom,adreno-gmu-740.1 <<
230 - qcom,adreno-gmu-750.1 <<
231 - qcom,adreno-gmu-x185.1 <<
232 then: <<
233 properties: <<
234 reg: <<
235 items: <<
236 - description: Core GMU registers <<
237 - description: Resource controller <<
238 - description: GMU PDC registers <<
239 reg-names: <<
240 items: <<
241 - const: gmu <<
242 - const: rscc <<
243 - const: gmu_pdc <<
244 clocks: <<
245 items: <<
246 - description: GPU AHB clock <<
247 - description: GMU clock <<
248 - description: GPU CX clock <<
249 - description: GPU AXI clock <<
250 - description: GPU MEMNOC clock <<
251 - description: GMU HUB clock <<
252 - description: GPUSS DEMET clock <<
253 clock-names: <<
254 items: <<
255 - const: ahb <<
256 - const: gmu <<
257 - const: cxo <<
258 - const: axi <<
259 - const: memnoc <<
260 - const: hub <<
261 - const: demet <<
262 <<
263 required: <<
264 - qcom,qmp <<
265 215
266 - if: 216 - if:
267 properties: 217 properties:
268 compatible: 218 compatible:
269 contains: 219 contains:
270 const: qcom,adreno-gmu-wrapper 220 const: qcom,adreno-gmu-wrapper
271 then: 221 then:
272 properties: 222 properties:
273 reg: 223 reg:
274 items: 224 items:
275 - description: GMU wrapper registe 225 - description: GMU wrapper register space
276 reg-names: 226 reg-names:
277 items: 227 items:
278 - const: gmu 228 - const: gmu
279 else: 229 else:
280 required: 230 required:
281 - clocks 231 - clocks
282 - clock-names 232 - clock-names
283 - interrupts 233 - interrupts
284 - interrupt-names 234 - interrupt-names
285 - iommus 235 - iommus
286 - operating-points-v2 236 - operating-points-v2
287 237
288 examples: 238 examples:
289 - | 239 - |
290 #include <dt-bindings/clock/qcom,gpucc-sdm 240 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
291 #include <dt-bindings/clock/qcom,gcc-sdm84 241 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
292 #include <dt-bindings/interrupt-controller 242 #include <dt-bindings/interrupt-controller/irq.h>
293 #include <dt-bindings/interrupt-controller 243 #include <dt-bindings/interrupt-controller/arm-gic.h>
294 244
295 gmu: gmu@506a000 { 245 gmu: gmu@506a000 {
296 compatible = "qcom,adreno-gmu-630.2", 246 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
297 247
298 reg = <0x506a000 0x30000>, 248 reg = <0x506a000 0x30000>,
299 <0xb280000 0x10000>, 249 <0xb280000 0x10000>,
300 <0xb480000 0x10000>; 250 <0xb480000 0x10000>;
301 reg-names = "gmu", "gmu_pdc", "gmu_pdc 251 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
302 252
303 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 253 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
304 <&gpucc GPU_CC_CXO_CLK>, 254 <&gpucc GPU_CC_CXO_CLK>,
305 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 255 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
306 <&gcc GCC_GPU_MEMNOC_GFX_CLK> 256 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
307 clock-names = "gmu", "cxo", "axi", "me 257 clock-names = "gmu", "cxo", "axi", "memnoc";
308 258
309 interrupts = <GIC_SPI 304 IRQ_TYPE_LEV 259 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 305 IRQ_TYPE_LEV 260 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
311 interrupt-names = "hfi", "gmu"; 261 interrupt-names = "hfi", "gmu";
312 262
313 power-domains = <&gpucc GPU_CX_GDSC>, 263 power-domains = <&gpucc GPU_CX_GDSC>,
314 <&gpucc GPU_GX_GDSC>; 264 <&gpucc GPU_GX_GDSC>;
315 power-domain-names = "cx", "gx"; 265 power-domain-names = "cx", "gx";
316 266
317 iommus = <&adreno_smmu 5>; 267 iommus = <&adreno_smmu 5>;
318 operating-points-v2 = <&gmu_opp_table> 268 operating-points-v2 = <&gmu_opp_table>;
319 }; 269 };
320 270
321 gmu_wrapper: gmu@596a000 { 271 gmu_wrapper: gmu@596a000 {
322 compatible = "qcom,adreno-gmu-wrapper" 272 compatible = "qcom,adreno-gmu-wrapper";
323 reg = <0x0596a000 0x30000>; 273 reg = <0x0596a000 0x30000>;
324 reg-names = "gmu"; 274 reg-names = "gmu";
325 power-domains = <&gpucc GPU_CX_GDSC>, 275 power-domains = <&gpucc GPU_CX_GDSC>,
326 <&gpucc GPU_GX_GDSC>; 276 <&gpucc GPU_GX_GDSC>;
327 power-domain-names = "cx", "gx"; 277 power-domain-names = "cx", "gx";
328 }; 278 };
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