1 # SPDX-License-Identifier: GPL-2.0-only 1 # SPDX-License-Identifier: GPL-2.0-only
2 # Copyright 2019-2020, The Linux Foundation, A 2 # Copyright 2019-2020, The Linux Foundation, All Rights Reserved
3 %YAML 1.2 3 %YAML 1.2
4 --- 4 ---
5 5
6 $id: http://devicetree.org/schemas/display/msm 6 $id: http://devicetree.org/schemas/display/msm/gmu.yaml#
7 $schema: http://devicetree.org/meta-schemas/co 7 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 8
9 title: GMU attached to certain Adreno GPUs 9 title: GMU attached to certain Adreno GPUs
10 10
11 maintainers: 11 maintainers:
12 - Rob Clark <robdclark@gmail.com> 12 - Rob Clark <robdclark@gmail.com>
13 13
14 description: | 14 description: |
15 These bindings describe the Graphics Managem 15 These bindings describe the Graphics Management Unit (GMU) that is attached
16 to members of the Adreno A6xx GPU family. Th 16 to members of the Adreno A6xx GPU family. The GMU provides on-device power
17 management and support to improve power effi 17 management and support to improve power efficiency and reduce the load on
18 the CPU. 18 the CPU.
19 19
20 properties: 20 properties:
21 compatible: 21 compatible:
22 oneOf: 22 oneOf:
23 - items: 23 - items:
24 - pattern: '^qcom,adreno-gmu-[67][0- 24 - pattern: '^qcom,adreno-gmu-[67][0-9][0-9]\.[0-9]$'
25 - const: qcom,adreno-gmu 25 - const: qcom,adreno-gmu
26 - items: <<
27 - pattern: '^qcom,adreno-gmu-x[1-9][ <<
28 - const: qcom,adreno-gmu <<
29 - const: qcom,adreno-gmu-wrapper 26 - const: qcom,adreno-gmu-wrapper
30 27
31 reg: 28 reg:
32 minItems: 1 29 minItems: 1
33 maxItems: 4 30 maxItems: 4
34 31
35 reg-names: 32 reg-names:
36 minItems: 1 33 minItems: 1
37 maxItems: 4 34 maxItems: 4
38 35
39 clocks: 36 clocks:
40 minItems: 4 37 minItems: 4
41 maxItems: 7 38 maxItems: 7
42 39
43 clock-names: 40 clock-names:
44 minItems: 4 41 minItems: 4
45 maxItems: 7 42 maxItems: 7
46 43
47 interrupts: 44 interrupts:
48 items: 45 items:
49 - description: GMU HFI interrupt 46 - description: GMU HFI interrupt
50 - description: GMU interrupt 47 - description: GMU interrupt
51 48
52 interrupt-names: 49 interrupt-names:
53 items: 50 items:
54 - const: hfi 51 - const: hfi
55 - const: gmu 52 - const: gmu
56 53
57 power-domains: 54 power-domains:
58 items: 55 items:
59 - description: CX power domain 56 - description: CX power domain
60 - description: GX power domain 57 - description: GX power domain
61 58
62 power-domain-names: 59 power-domain-names:
63 items: 60 items:
64 - const: cx 61 - const: cx
65 - const: gx 62 - const: gx
66 63
67 iommus: 64 iommus:
68 maxItems: 1 65 maxItems: 1
69 66
70 qcom,qmp: 67 qcom,qmp:
71 $ref: /schemas/types.yaml#/definitions/pha 68 $ref: /schemas/types.yaml#/definitions/phandle
72 description: Reference to the AOSS side-ch 69 description: Reference to the AOSS side-channel message RAM
73 70
74 operating-points-v2: true 71 operating-points-v2: true
75 72
76 opp-table: 73 opp-table:
77 type: object 74 type: object
78 75
79 required: 76 required:
80 - compatible 77 - compatible
81 - reg 78 - reg
82 - reg-names 79 - reg-names
83 - power-domains 80 - power-domains
84 - power-domain-names 81 - power-domain-names
85 82
86 additionalProperties: false 83 additionalProperties: false
87 84
88 allOf: 85 allOf:
89 - if: 86 - if:
90 properties: 87 properties:
91 compatible: 88 compatible:
92 contains: 89 contains:
93 enum: 90 enum:
94 - qcom,adreno-gmu-618.0 91 - qcom,adreno-gmu-618.0
95 - qcom,adreno-gmu-630.2 92 - qcom,adreno-gmu-630.2
96 then: 93 then:
97 properties: 94 properties:
98 reg: 95 reg:
99 items: 96 items:
100 - description: Core GMU registers 97 - description: Core GMU registers
101 - description: GMU PDC registers 98 - description: GMU PDC registers
102 - description: GMU PDC sequence re 99 - description: GMU PDC sequence registers
103 reg-names: 100 reg-names:
104 items: 101 items:
105 - const: gmu 102 - const: gmu
106 - const: gmu_pdc 103 - const: gmu_pdc
107 - const: gmu_pdc_seq 104 - const: gmu_pdc_seq
108 clocks: 105 clocks:
109 items: 106 items:
110 - description: GMU clock 107 - description: GMU clock
111 - description: GPU CX clock 108 - description: GPU CX clock
112 - description: GPU AXI clock 109 - description: GPU AXI clock
113 - description: GPU MEMNOC clock 110 - description: GPU MEMNOC clock
114 clock-names: 111 clock-names:
115 items: 112 items:
116 - const: gmu 113 - const: gmu
117 - const: cxo 114 - const: cxo
118 - const: axi 115 - const: axi
119 - const: memnoc 116 - const: memnoc
120 117
121 - if: 118 - if:
122 properties: 119 properties:
123 compatible: 120 compatible:
124 contains: 121 contains:
125 enum: 122 enum:
126 - qcom,adreno-gmu-635.0 123 - qcom,adreno-gmu-635.0
127 - qcom,adreno-gmu-660.1 124 - qcom,adreno-gmu-660.1
128 then: 125 then:
129 properties: 126 properties:
130 reg: 127 reg:
131 items: 128 items:
132 - description: Core GMU registers 129 - description: Core GMU registers
133 - description: Resource controller 130 - description: Resource controller registers
134 - description: GMU PDC registers 131 - description: GMU PDC registers
135 reg-names: 132 reg-names:
136 items: 133 items:
137 - const: gmu 134 - const: gmu
138 - const: rscc 135 - const: rscc
139 - const: gmu_pdc 136 - const: gmu_pdc
140 clocks: 137 clocks:
141 items: 138 items:
142 - description: GMU clock 139 - description: GMU clock
143 - description: GPU CX clock 140 - description: GPU CX clock
144 - description: GPU AXI clock 141 - description: GPU AXI clock
145 - description: GPU MEMNOC clock 142 - description: GPU MEMNOC clock
146 - description: GPU AHB clock 143 - description: GPU AHB clock
147 - description: GPU HUB CX clock 144 - description: GPU HUB CX clock
148 - description: GPU SMMU vote clock 145 - description: GPU SMMU vote clock
149 clock-names: 146 clock-names:
150 items: 147 items:
151 - const: gmu 148 - const: gmu
152 - const: cxo 149 - const: cxo
153 - const: axi 150 - const: axi
154 - const: memnoc 151 - const: memnoc
155 - const: ahb 152 - const: ahb
156 - const: hub 153 - const: hub
157 - const: smmu_vote 154 - const: smmu_vote
158 155
159 - if: 156 - if:
160 properties: 157 properties:
161 compatible: 158 compatible:
162 contains: 159 contains:
163 enum: 160 enum:
164 - qcom,adreno-gmu-640.1 161 - qcom,adreno-gmu-640.1
165 then: 162 then:
166 properties: 163 properties:
167 reg: 164 reg:
168 items: 165 items:
169 - description: Core GMU registers 166 - description: Core GMU registers
170 - description: GMU PDC registers 167 - description: GMU PDC registers
171 - description: GMU PDC sequence re 168 - description: GMU PDC sequence registers
172 reg-names: 169 reg-names:
173 items: 170 items:
174 - const: gmu 171 - const: gmu
175 - const: gmu_pdc 172 - const: gmu_pdc
176 - const: gmu_pdc_seq 173 - const: gmu_pdc_seq
177 174
178 - if: 175 - if:
179 properties: 176 properties:
180 compatible: 177 compatible:
181 contains: 178 contains:
182 enum: 179 enum:
183 - qcom,adreno-gmu-650.2 180 - qcom,adreno-gmu-650.2
184 then: 181 then:
185 properties: 182 properties:
186 reg: 183 reg:
187 items: 184 items:
188 - description: Core GMU registers 185 - description: Core GMU registers
189 - description: Resource controller 186 - description: Resource controller registers
190 - description: GMU PDC registers 187 - description: GMU PDC registers
191 - description: GMU PDC sequence re 188 - description: GMU PDC sequence registers
192 reg-names: 189 reg-names:
193 items: 190 items:
194 - const: gmu 191 - const: gmu
195 - const: rscc 192 - const: rscc
196 - const: gmu_pdc 193 - const: gmu_pdc
197 - const: gmu_pdc_seq 194 - const: gmu_pdc_seq
198 195
199 - if: 196 - if:
200 properties: 197 properties:
201 compatible: 198 compatible:
202 contains: 199 contains:
203 enum: 200 enum:
204 - qcom,adreno-gmu-640.1 201 - qcom,adreno-gmu-640.1
205 - qcom,adreno-gmu-650.2 202 - qcom,adreno-gmu-650.2
206 then: 203 then:
207 properties: 204 properties:
208 clocks: 205 clocks:
209 items: 206 items:
210 - description: GPU AHB clock 207 - description: GPU AHB clock
211 - description: GMU clock 208 - description: GMU clock
212 - description: GPU CX clock 209 - description: GPU CX clock
213 - description: GPU AXI clock 210 - description: GPU AXI clock
214 - description: GPU MEMNOC clock 211 - description: GPU MEMNOC clock
215 clock-names: 212 clock-names:
216 items: 213 items:
217 - const: ahb 214 - const: ahb
218 - const: gmu 215 - const: gmu
219 - const: cxo 216 - const: cxo
220 - const: axi 217 - const: axi
221 - const: memnoc 218 - const: memnoc
222 219
223 - if: 220 - if:
224 properties: 221 properties:
225 compatible: 222 compatible:
226 contains: 223 contains:
227 enum: 224 enum:
228 - qcom,adreno-gmu-730.1 225 - qcom,adreno-gmu-730.1
229 - qcom,adreno-gmu-740.1 226 - qcom,adreno-gmu-740.1
230 - qcom,adreno-gmu-750.1 <<
231 - qcom,adreno-gmu-x185.1 <<
232 then: 227 then:
233 properties: 228 properties:
234 reg: 229 reg:
235 items: 230 items:
236 - description: Core GMU registers 231 - description: Core GMU registers
237 - description: Resource controller 232 - description: Resource controller registers
238 - description: GMU PDC registers 233 - description: GMU PDC registers
239 reg-names: 234 reg-names:
240 items: 235 items:
241 - const: gmu 236 - const: gmu
242 - const: rscc 237 - const: rscc
243 - const: gmu_pdc 238 - const: gmu_pdc
244 clocks: 239 clocks:
245 items: 240 items:
246 - description: GPU AHB clock 241 - description: GPU AHB clock
247 - description: GMU clock 242 - description: GMU clock
248 - description: GPU CX clock 243 - description: GPU CX clock
249 - description: GPU AXI clock 244 - description: GPU AXI clock
250 - description: GPU MEMNOC clock 245 - description: GPU MEMNOC clock
251 - description: GMU HUB clock 246 - description: GMU HUB clock
252 - description: GPUSS DEMET clock 247 - description: GPUSS DEMET clock
253 clock-names: 248 clock-names:
254 items: 249 items:
255 - const: ahb 250 - const: ahb
256 - const: gmu 251 - const: gmu
257 - const: cxo 252 - const: cxo
258 - const: axi 253 - const: axi
259 - const: memnoc 254 - const: memnoc
260 - const: hub 255 - const: hub
261 - const: demet 256 - const: demet
262 257
263 required: 258 required:
264 - qcom,qmp 259 - qcom,qmp
265 260
266 - if: 261 - if:
267 properties: 262 properties:
268 compatible: 263 compatible:
269 contains: 264 contains:
270 const: qcom,adreno-gmu-wrapper 265 const: qcom,adreno-gmu-wrapper
271 then: 266 then:
272 properties: 267 properties:
273 reg: 268 reg:
274 items: 269 items:
275 - description: GMU wrapper registe 270 - description: GMU wrapper register space
276 reg-names: 271 reg-names:
277 items: 272 items:
278 - const: gmu 273 - const: gmu
279 else: 274 else:
280 required: 275 required:
281 - clocks 276 - clocks
282 - clock-names 277 - clock-names
283 - interrupts 278 - interrupts
284 - interrupt-names 279 - interrupt-names
285 - iommus 280 - iommus
286 - operating-points-v2 281 - operating-points-v2
287 282
288 examples: 283 examples:
289 - | 284 - |
290 #include <dt-bindings/clock/qcom,gpucc-sdm 285 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
291 #include <dt-bindings/clock/qcom,gcc-sdm84 286 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
292 #include <dt-bindings/interrupt-controller 287 #include <dt-bindings/interrupt-controller/irq.h>
293 #include <dt-bindings/interrupt-controller 288 #include <dt-bindings/interrupt-controller/arm-gic.h>
294 289
295 gmu: gmu@506a000 { 290 gmu: gmu@506a000 {
296 compatible = "qcom,adreno-gmu-630.2", 291 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
297 292
298 reg = <0x506a000 0x30000>, 293 reg = <0x506a000 0x30000>,
299 <0xb280000 0x10000>, 294 <0xb280000 0x10000>,
300 <0xb480000 0x10000>; 295 <0xb480000 0x10000>;
301 reg-names = "gmu", "gmu_pdc", "gmu_pdc 296 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
302 297
303 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 298 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
304 <&gpucc GPU_CC_CXO_CLK>, 299 <&gpucc GPU_CC_CXO_CLK>,
305 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 300 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
306 <&gcc GCC_GPU_MEMNOC_GFX_CLK> 301 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
307 clock-names = "gmu", "cxo", "axi", "me 302 clock-names = "gmu", "cxo", "axi", "memnoc";
308 303
309 interrupts = <GIC_SPI 304 IRQ_TYPE_LEV 304 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 305 IRQ_TYPE_LEV 305 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
311 interrupt-names = "hfi", "gmu"; 306 interrupt-names = "hfi", "gmu";
312 307
313 power-domains = <&gpucc GPU_CX_GDSC>, 308 power-domains = <&gpucc GPU_CX_GDSC>,
314 <&gpucc GPU_GX_GDSC>; 309 <&gpucc GPU_GX_GDSC>;
315 power-domain-names = "cx", "gx"; 310 power-domain-names = "cx", "gx";
316 311
317 iommus = <&adreno_smmu 5>; 312 iommus = <&adreno_smmu 5>;
318 operating-points-v2 = <&gmu_opp_table> 313 operating-points-v2 = <&gmu_opp_table>;
319 }; 314 };
320 315
321 gmu_wrapper: gmu@596a000 { 316 gmu_wrapper: gmu@596a000 {
322 compatible = "qcom,adreno-gmu-wrapper" 317 compatible = "qcom,adreno-gmu-wrapper";
323 reg = <0x0596a000 0x30000>; 318 reg = <0x0596a000 0x30000>;
324 reg-names = "gmu"; 319 reg-names = "gmu";
325 power-domains = <&gpucc GPU_CX_GDSC>, 320 power-domains = <&gpucc GPU_CX_GDSC>,
326 <&gpucc GPU_GX_GDSC>; 321 <&gpucc GPU_GX_GDSC>;
327 power-domain-names = "cx", "gx"; 322 power-domain-names = "cx", "gx";
328 }; 323 };
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