1 # SPDX-License-Identifier: GPL-2.0-only OR BSD !! 1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/display/msm 4 $id: http://devicetree.org/schemas/display/msm/mdss-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Qualcomm Display MDSS common properties 7 title: Qualcomm Display MDSS common properties
8 8
9 maintainers: 9 maintainers:
10 - Krishna Manikandan <quic_mkrishn@quicinc.co 10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
11 - Dmitry Baryshkov <dmitry.baryshkov@linaro.o 11 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
12 - Rob Clark <robdclark@gmail.com> 12 - Rob Clark <robdclark@gmail.com>
13 13
14 description: 14 description:
15 Device tree bindings for MSM Mobile Display 15 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
16 sub-blocks like DPU display controller, DSI 16 sub-blocks like DPU display controller, DSI and DP interfaces etc.
17 17
18 # Do not select this by default, otherwise it <<
19 # devices. <<
20 select: <<
21 false <<
22 <<
23 properties: 18 properties:
24 $nodename: <<
25 pattern: "^display-subsystem@[0-9a-f]+$" <<
26 <<
27 reg: 19 reg:
28 maxItems: 1 20 maxItems: 1
29 21
30 reg-names: 22 reg-names:
31 const: mdss 23 const: mdss
32 24
33 power-domains: 25 power-domains:
34 maxItems: 1 26 maxItems: 1
35 27
36 clocks: 28 clocks:
37 minItems: 2 29 minItems: 2
38 maxItems: 4 30 maxItems: 4
39 31
40 clock-names: 32 clock-names:
41 minItems: 2 33 minItems: 2
42 maxItems: 4 34 maxItems: 4
43 35
44 interrupts: 36 interrupts:
45 maxItems: 1 37 maxItems: 1
46 38
47 interrupt-controller: true 39 interrupt-controller: true
48 40
49 "#address-cells": true 41 "#address-cells": true
50 42
51 "#size-cells": true 43 "#size-cells": true
52 44
53 "#interrupt-cells": 45 "#interrupt-cells":
54 const: 1 46 const: 1
55 47
56 iommus: 48 iommus:
57 minItems: 1 49 minItems: 1
58 items: 50 items:
59 - description: Phandle to apps_smmu node 51 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
60 - description: Phandle to apps_smmu node 52 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
61 53
62 ranges: true 54 ranges: true
63 55
64 # This is not a perfect description, but it' <<
65 # the entries like we do with interconnect-n <<
66 interconnects: 56 interconnects:
67 minItems: 1 57 minItems: 1
68 items: 58 items:
69 - description: Interconnect path from md 59 - description: Interconnect path from mdp0 (or a single mdp) port to the data bus
70 - description: Interconnect path from md 60 - description: Interconnect path from mdp1 port to the data bus
71 - description: Interconnect path from CP <<
72 61
73 interconnect-names: 62 interconnect-names:
74 oneOf: !! 63 minItems: 1
75 - minItems: 1 !! 64 items:
76 items: !! 65 - const: mdp0-mem
77 - const: mdp0-mem !! 66 - const: mdp1-mem
78 - const: cpu-cfg <<
79 <<
80 - minItems: 2 <<
81 items: <<
82 - const: mdp0-mem <<
83 - const: mdp1-mem <<
84 - const: cpu-cfg <<
85 67
86 resets: 68 resets:
87 items: 69 items:
88 - description: MDSS_CORE reset 70 - description: MDSS_CORE reset
89 71
90 memory-region: <<
91 maxItems: 1 <<
92 description: <<
93 Phandle to a node describing a reserved <<
94 For example, the splash memory region se <<
95 <<
96 required: 72 required:
>> 73 - compatible
97 - reg 74 - reg
98 - reg-names 75 - reg-names
99 - power-domains 76 - power-domains
100 - clocks 77 - clocks
101 - interrupts 78 - interrupts
102 - interrupt-controller 79 - interrupt-controller
103 - iommus 80 - iommus
104 - ranges 81 - ranges
105 82
106 additionalProperties: true 83 additionalProperties: true
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