1 # SPDX-License-Identifier: GPL-2.0-only OR BSD 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/display/msm 4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7280-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Qualcomm SC7280 Display MDSS 7 title: Qualcomm SC7280 Display MDSS
8 8
9 maintainers: 9 maintainers:
10 - Krishna Manikandan <quic_mkrishn@quicinc.co 10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
11 11
12 description: 12 description:
13 Device tree bindings for MSM Mobile Display 13 Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates
14 sub-blocks like DPU display controller, DSI 14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15 bindings of MDSS are mentioned for SC7280. 15 bindings of MDSS are mentioned for SC7280.
16 16
17 $ref: /schemas/display/msm/mdss-common.yaml# 17 $ref: /schemas/display/msm/mdss-common.yaml#
18 18
19 properties: 19 properties:
20 compatible: 20 compatible:
21 const: qcom,sc7280-mdss 21 const: qcom,sc7280-mdss
22 22
23 clocks: 23 clocks:
24 items: 24 items:
25 - description: Display AHB clock from gc 25 - description: Display AHB clock from gcc
26 - description: Display AHB clock from di 26 - description: Display AHB clock from dispcc
27 - description: Display core clock 27 - description: Display core clock
28 28
29 clock-names: 29 clock-names:
30 items: 30 items:
31 - const: iface 31 - const: iface
32 - const: ahb 32 - const: ahb
33 - const: core 33 - const: core
34 34
35 iommus: 35 iommus:
36 maxItems: 1 36 maxItems: 1
37 37
38 interconnects: 38 interconnects:
39 items: 39 items:
40 - description: Interconnect path from md 40 - description: Interconnect path from mdp0 port to the data bus
41 - description: Interconnect path from CP 41 - description: Interconnect path from CPU to the reg bus
42 42
43 interconnect-names: 43 interconnect-names:
44 items: 44 items:
45 - const: mdp0-mem 45 - const: mdp0-mem
46 - const: cpu-cfg 46 - const: cpu-cfg
47 47
48 patternProperties: 48 patternProperties:
49 "^display-controller@[0-9a-f]+$": 49 "^display-controller@[0-9a-f]+$":
50 type: object 50 type: object
51 additionalProperties: true 51 additionalProperties: true
52 52
53 properties: 53 properties:
54 compatible: 54 compatible:
55 const: qcom,sc7280-dpu 55 const: qcom,sc7280-dpu
56 56
57 "^displayport-controller@[0-9a-f]+$": 57 "^displayport-controller@[0-9a-f]+$":
58 type: object 58 type: object
59 additionalProperties: true 59 additionalProperties: true
60 60
61 properties: 61 properties:
62 compatible: 62 compatible:
63 const: qcom,sc7280-dp 63 const: qcom,sc7280-dp
64 64
65 "^dsi@[0-9a-f]+$": 65 "^dsi@[0-9a-f]+$":
66 type: object 66 type: object
67 additionalProperties: true 67 additionalProperties: true
68 68
69 properties: 69 properties:
70 compatible: 70 compatible:
71 items: 71 items:
72 - const: qcom,sc7280-dsi-ctrl 72 - const: qcom,sc7280-dsi-ctrl
73 - const: qcom,mdss-dsi-ctrl 73 - const: qcom,mdss-dsi-ctrl
74 74
75 "^edp@[0-9a-f]+$": 75 "^edp@[0-9a-f]+$":
76 type: object 76 type: object
77 additionalProperties: true 77 additionalProperties: true
78 78
79 properties: 79 properties:
80 compatible: 80 compatible:
81 const: qcom,sc7280-edp 81 const: qcom,sc7280-edp
82 82
83 "^phy@[0-9a-f]+$": 83 "^phy@[0-9a-f]+$":
84 type: object 84 type: object
85 additionalProperties: true 85 additionalProperties: true
86 86
87 properties: 87 properties:
88 compatible: 88 compatible:
89 enum: 89 enum:
90 - qcom,sc7280-dsi-phy-7nm 90 - qcom,sc7280-dsi-phy-7nm
91 - qcom,sc7280-edp-phy 91 - qcom,sc7280-edp-phy
92 92
93 required: 93 required:
94 - compatible 94 - compatible
95 95
96 unevaluatedProperties: false 96 unevaluatedProperties: false
97 97
98 examples: 98 examples:
99 - | 99 - |
100 #include <dt-bindings/clock/qcom,dispcc-sc 100 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
101 #include <dt-bindings/clock/qcom,gcc-sc728 101 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
102 #include <dt-bindings/clock/qcom,rpmh.h> 102 #include <dt-bindings/clock/qcom,rpmh.h>
103 #include <dt-bindings/interrupt-controller 103 #include <dt-bindings/interrupt-controller/arm-gic.h>
104 #include <dt-bindings/interconnect/qcom,sc 104 #include <dt-bindings/interconnect/qcom,sc7280.h>
105 #include <dt-bindings/power/qcom-rpmpd.h> 105 #include <dt-bindings/power/qcom-rpmpd.h>
106 106
107 display-subsystem@ae00000 { 107 display-subsystem@ae00000 {
108 #address-cells = <1>; 108 #address-cells = <1>;
109 #size-cells = <1>; 109 #size-cells = <1>;
110 compatible = "qcom,sc7280-mdss"; 110 compatible = "qcom,sc7280-mdss";
111 reg = <0xae00000 0x1000>; 111 reg = <0xae00000 0x1000>;
112 reg-names = "mdss"; 112 reg-names = "mdss";
113 power-domains = <&dispcc DISP_CC_MDSS_ 113 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
114 clocks = <&gcc GCC_DISP_AHB_CLK>, 114 clocks = <&gcc GCC_DISP_AHB_CLK>,
115 <&dispcc DISP_CC_MDSS_AHB_CLK 115 <&dispcc DISP_CC_MDSS_AHB_CLK>,
116 <&dispcc DISP_CC_MDSS_MDP_CLK 116 <&dispcc DISP_CC_MDSS_MDP_CLK>;
117 clock-names = "iface", 117 clock-names = "iface",
118 "ahb", 118 "ahb",
119 "core"; 119 "core";
120 120
121 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVE 121 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
122 interrupt-controller; 122 interrupt-controller;
123 #interrupt-cells = <1>; 123 #interrupt-cells = <1>;
124 124
125 interconnects = <&mmss_noc MASTER_MDP0 125 interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>,
126 <&gem_noc MASTER_APPSS 126 <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_DISPLAY_CFG>;
127 interconnect-names = "mdp0-mem", 127 interconnect-names = "mdp0-mem",
128 "cpu-cfg"; 128 "cpu-cfg";
129 129
130 iommus = <&apps_smmu 0x900 0x402>; 130 iommus = <&apps_smmu 0x900 0x402>;
131 ranges; 131 ranges;
132 132
133 display-controller@ae01000 { 133 display-controller@ae01000 {
134 compatible = "qcom,sc7280-dpu"; 134 compatible = "qcom,sc7280-dpu";
135 reg = <0x0ae01000 0x8f000>, 135 reg = <0x0ae01000 0x8f000>,
136 <0x0aeb0000 0x2008>; 136 <0x0aeb0000 0x2008>;
137 137
138 reg-names = "mdp", "vbif"; 138 reg-names = "mdp", "vbif";
139 139
140 clocks = <&gcc GCC_DISP_HF_AXI_CLK 140 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
141 <&gcc GCC_DISP_SF_AXI_CLK 141 <&gcc GCC_DISP_SF_AXI_CLK>,
142 <&dispcc DISP_CC_MDSS_AHB 142 <&dispcc DISP_CC_MDSS_AHB_CLK>,
143 <&dispcc DISP_CC_MDSS_MDP 143 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
144 <&dispcc DISP_CC_MDSS_MDP 144 <&dispcc DISP_CC_MDSS_MDP_CLK>,
145 <&dispcc DISP_CC_MDSS_VSY 145 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
146 clock-names = "bus", 146 clock-names = "bus",
147 "nrt_bus", 147 "nrt_bus",
148 "iface", 148 "iface",
149 "lut", 149 "lut",
150 "core", 150 "core",
151 "vsync"; 151 "vsync";
152 152
153 interrupt-parent = <&mdss>; 153 interrupt-parent = <&mdss>;
154 interrupts = <0>; 154 interrupts = <0>;
155 power-domains = <&rpmhpd SC7280_CX 155 power-domains = <&rpmhpd SC7280_CX>;
156 operating-points-v2 = <&mdp_opp_ta 156 operating-points-v2 = <&mdp_opp_table>;
157 157
158 ports { 158 ports {
159 #address-cells = <1>; 159 #address-cells = <1>;
160 #size-cells = <0>; 160 #size-cells = <0>;
161 161
162 port@0 { 162 port@0 {
163 reg = <0>; 163 reg = <0>;
164 dpu_intf1_out: endpoint { 164 dpu_intf1_out: endpoint {
165 remote-endpoint = <&ds 165 remote-endpoint = <&dsi0_in>;
166 }; 166 };
167 }; 167 };
168 168
169 port@1 { 169 port@1 {
170 reg = <1>; 170 reg = <1>;
171 dpu_intf5_out: endpoint { 171 dpu_intf5_out: endpoint {
172 remote-endpoint = <&ed 172 remote-endpoint = <&edp_in>;
173 }; 173 };
174 }; 174 };
175 175
176 port@2 { 176 port@2 {
177 reg = <2>; 177 reg = <2>;
178 dpu_intf0_out: endpoint { 178 dpu_intf0_out: endpoint {
179 remote-endpoint = <&dp 179 remote-endpoint = <&dp_in>;
180 }; 180 };
181 }; 181 };
182 }; 182 };
183 }; 183 };
184 184
185 dsi@ae94000 { 185 dsi@ae94000 {
186 compatible = "qcom,sc7280-dsi-ctrl 186 compatible = "qcom,sc7280-dsi-ctrl", "qcom,mdss-dsi-ctrl";
187 reg = <0x0ae94000 0x400>; 187 reg = <0x0ae94000 0x400>;
188 reg-names = "dsi_ctrl"; 188 reg-names = "dsi_ctrl";
189 189
190 interrupt-parent = <&mdss>; 190 interrupt-parent = <&mdss>;
191 interrupts = <4>; 191 interrupts = <4>;
192 192
193 clocks = <&dispcc DISP_CC_MDSS_BYT 193 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
194 <&dispcc DISP_CC_MDSS_BYT 194 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
195 <&dispcc DISP_CC_MDSS_PCL 195 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
196 <&dispcc DISP_CC_MDSS_ESC 196 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
197 <&dispcc DISP_CC_MDSS_AHB 197 <&dispcc DISP_CC_MDSS_AHB_CLK>,
198 <&gcc GCC_DISP_HF_AXI_CLK 198 <&gcc GCC_DISP_HF_AXI_CLK>;
199 clock-names = "byte", 199 clock-names = "byte",
200 "byte_intf", 200 "byte_intf",
201 "pixel", 201 "pixel",
202 "core", 202 "core",
203 "iface", 203 "iface",
204 "bus"; 204 "bus";
205 205
206 assigned-clocks = <&dispcc DISP_CC 206 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
207 <&dispcc DISP_CC 207 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
208 assigned-clock-parents = <&mdss_ds 208 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>;
209 209
210 operating-points-v2 = <&dsi_opp_ta 210 operating-points-v2 = <&dsi_opp_table>;
211 power-domains = <&rpmhpd SC7280_CX 211 power-domains = <&rpmhpd SC7280_CX>;
212 212
213 phys = <&mdss_dsi_phy>; 213 phys = <&mdss_dsi_phy>;
214 phy-names = "dsi"; 214 phy-names = "dsi";
215 215
216 #address-cells = <1>; 216 #address-cells = <1>;
217 #size-cells = <0>; 217 #size-cells = <0>;
218 218
219 ports { 219 ports {
220 #address-cells = <1>; 220 #address-cells = <1>;
221 #size-cells = <0>; 221 #size-cells = <0>;
222 222
223 port@0 { 223 port@0 {
224 reg = <0>; 224 reg = <0>;
225 dsi0_in: endpoint { 225 dsi0_in: endpoint {
226 remote-endpoint = <&dp 226 remote-endpoint = <&dpu_intf1_out>;
227 }; 227 };
228 }; 228 };
229 229
230 port@1 { 230 port@1 {
231 reg = <1>; 231 reg = <1>;
232 dsi0_out: endpoint { 232 dsi0_out: endpoint {
233 }; 233 };
234 }; 234 };
235 }; 235 };
236 236
237 dsi_opp_table: opp-table { 237 dsi_opp_table: opp-table {
238 compatible = "operating-points 238 compatible = "operating-points-v2";
239 239
240 opp-187500000 { 240 opp-187500000 {
241 opp-hz = /bits/ 64 <187500 241 opp-hz = /bits/ 64 <187500000>;
242 required-opps = <&rpmhpd_o 242 required-opps = <&rpmhpd_opp_low_svs>;
243 }; 243 };
244 244
245 opp-300000000 { 245 opp-300000000 {
246 opp-hz = /bits/ 64 <300000 246 opp-hz = /bits/ 64 <300000000>;
247 required-opps = <&rpmhpd_o 247 required-opps = <&rpmhpd_opp_svs>;
248 }; 248 };
249 249
250 opp-358000000 { 250 opp-358000000 {
251 opp-hz = /bits/ 64 <358000 251 opp-hz = /bits/ 64 <358000000>;
252 required-opps = <&rpmhpd_o 252 required-opps = <&rpmhpd_opp_svs_l1>;
253 }; 253 };
254 }; 254 };
255 }; 255 };
256 256
257 mdss_dsi_phy: phy@ae94400 { 257 mdss_dsi_phy: phy@ae94400 {
258 compatible = "qcom,sc7280-dsi-phy- 258 compatible = "qcom,sc7280-dsi-phy-7nm";
259 reg = <0x0ae94400 0x200>, 259 reg = <0x0ae94400 0x200>,
260 <0x0ae94600 0x280>, 260 <0x0ae94600 0x280>,
261 <0x0ae94900 0x280>; 261 <0x0ae94900 0x280>;
262 reg-names = "dsi_phy", 262 reg-names = "dsi_phy",
263 "dsi_phy_lane", 263 "dsi_phy_lane",
264 "dsi_pll"; 264 "dsi_pll";
265 265
266 #clock-cells = <1>; 266 #clock-cells = <1>;
267 #phy-cells = <0>; 267 #phy-cells = <0>;
268 268
269 clocks = <&dispcc DISP_CC_MDSS_AHB 269 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
270 <&rpmhcc RPMH_CXO_CLK>; 270 <&rpmhcc RPMH_CXO_CLK>;
271 clock-names = "iface", "ref"; 271 clock-names = "iface", "ref";
272 272
273 vdds-supply = <&vreg_dsi_supply>; 273 vdds-supply = <&vreg_dsi_supply>;
274 }; 274 };
275 275
276 edp@aea0000 { 276 edp@aea0000 {
277 compatible = "qcom,sc7280-edp"; 277 compatible = "qcom,sc7280-edp";
278 pinctrl-names = "default"; 278 pinctrl-names = "default";
279 pinctrl-0 = <&edp_hot_plug_det>; 279 pinctrl-0 = <&edp_hot_plug_det>;
280 280
281 reg = <0xaea0000 0x200>, 281 reg = <0xaea0000 0x200>,
282 <0xaea0200 0x200>, 282 <0xaea0200 0x200>,
283 <0xaea0400 0xc00>, 283 <0xaea0400 0xc00>,
284 <0xaea1000 0x400>; 284 <0xaea1000 0x400>;
285 285
286 interrupt-parent = <&mdss>; 286 interrupt-parent = <&mdss>;
287 interrupts = <14>; 287 interrupts = <14>;
288 288
289 clocks = <&dispcc DISP_CC_MDSS_AHB 289 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
290 <&dispcc DISP_CC_MDSS_EDP 290 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
291 <&dispcc DISP_CC_MDSS_EDP 291 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>,
292 <&dispcc DISP_CC_MDSS_EDP 292 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
293 <&dispcc DISP_CC_MDSS_EDP 293 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>;
294 clock-names = "core_iface", 294 clock-names = "core_iface",
295 "core_aux", 295 "core_aux",
296 "ctrl_link", 296 "ctrl_link",
297 "ctrl_link_iface", 297 "ctrl_link_iface",
298 "stream_pixel"; 298 "stream_pixel";
299 assigned-clocks = <&dispcc DISP_CC 299 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
300 <&dispcc DISP_CC 300 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
301 assigned-clock-parents = <&mdss_ed 301 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
302 302
303 phys = <&mdss_edp_phy>; 303 phys = <&mdss_edp_phy>;
304 phy-names = "dp"; 304 phy-names = "dp";
305 305
306 operating-points-v2 = <&edp_opp_ta 306 operating-points-v2 = <&edp_opp_table>;
307 power-domains = <&rpmhpd SC7280_CX 307 power-domains = <&rpmhpd SC7280_CX>;
308 308
309 ports { 309 ports {
310 #address-cells = <1>; 310 #address-cells = <1>;
311 #size-cells = <0>; 311 #size-cells = <0>;
312 312
313 port@0 { 313 port@0 {
314 reg = <0>; 314 reg = <0>;
315 edp_in: endpoint { 315 edp_in: endpoint {
316 remote-endpoint = <&dp 316 remote-endpoint = <&dpu_intf5_out>;
317 }; 317 };
318 }; 318 };
319 319
320 port@1 { 320 port@1 {
321 reg = <1>; 321 reg = <1>;
322 mdss_edp_out: endpoint { } 322 mdss_edp_out: endpoint { };
323 }; 323 };
324 }; 324 };
325 325
326 edp_opp_table: opp-table { 326 edp_opp_table: opp-table {
327 compatible = "operating-points 327 compatible = "operating-points-v2";
328 328
329 opp-160000000 { 329 opp-160000000 {
330 opp-hz = /bits/ 64 <160000 330 opp-hz = /bits/ 64 <160000000>;
331 required-opps = <&rpmhpd_o 331 required-opps = <&rpmhpd_opp_low_svs>;
332 }; 332 };
333 333
334 opp-270000000 { 334 opp-270000000 {
335 opp-hz = /bits/ 64 <270000 335 opp-hz = /bits/ 64 <270000000>;
336 required-opps = <&rpmhpd_o 336 required-opps = <&rpmhpd_opp_svs>;
337 }; 337 };
338 338
339 opp-540000000 { 339 opp-540000000 {
340 opp-hz = /bits/ 64 <540000 340 opp-hz = /bits/ 64 <540000000>;
341 required-opps = <&rpmhpd_o 341 required-opps = <&rpmhpd_opp_nom>;
342 }; 342 };
343 343
344 opp-810000000 { 344 opp-810000000 {
345 opp-hz = /bits/ 64 <810000 345 opp-hz = /bits/ 64 <810000000>;
346 required-opps = <&rpmhpd_o 346 required-opps = <&rpmhpd_opp_nom>;
347 }; 347 };
348 }; 348 };
349 }; 349 };
350 350
351 mdss_edp_phy: phy@aec2a00 { 351 mdss_edp_phy: phy@aec2a00 {
352 compatible = "qcom,sc7280-edp-phy" 352 compatible = "qcom,sc7280-edp-phy";
353 353
354 reg = <0xaec2a00 0x19c>, 354 reg = <0xaec2a00 0x19c>,
355 <0xaec2200 0xa0>, 355 <0xaec2200 0xa0>,
356 <0xaec2600 0xa0>, 356 <0xaec2600 0xa0>,
357 <0xaec2000 0x1c0>; 357 <0xaec2000 0x1c0>;
358 358
359 clocks = <&rpmhcc RPMH_CXO_CLK>, 359 clocks = <&rpmhcc RPMH_CXO_CLK>,
360 <&gcc GCC_EDP_CLKREF_EN>; 360 <&gcc GCC_EDP_CLKREF_EN>;
361 clock-names = "aux", 361 clock-names = "aux",
362 "cfg_ahb"; 362 "cfg_ahb";
363 363
364 #clock-cells = <1>; 364 #clock-cells = <1>;
365 #phy-cells = <0>; 365 #phy-cells = <0>;
366 }; 366 };
367 367
368 displayport-controller@ae90000 { 368 displayport-controller@ae90000 {
369 compatible = "qcom,sc7280-dp"; 369 compatible = "qcom,sc7280-dp";
370 370
371 reg = <0xae90000 0x200>, 371 reg = <0xae90000 0x200>,
372 <0xae90200 0x200>, 372 <0xae90200 0x200>,
373 <0xae90400 0xc00>, 373 <0xae90400 0xc00>,
374 <0xae91000 0x400>, 374 <0xae91000 0x400>,
375 <0xae91400 0x400>; 375 <0xae91400 0x400>;
376 376
377 interrupt-parent = <&mdss>; 377 interrupt-parent = <&mdss>;
378 interrupts = <12>; 378 interrupts = <12>;
379 379
380 clocks = <&dispcc DISP_CC_MDSS_AHB 380 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
381 <&dispcc DISP_CC_MDSS_DP_ 381 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
382 <&dispcc DISP_CC_MDSS_DP_ 382 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
383 <&dispcc DISP_CC_MDSS_DP_ 383 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
384 <&dispcc DISP_CC_MDSS_DP_ 384 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
385 clock-names = "core_iface", 385 clock-names = "core_iface",
386 "core_aux", 386 "core_aux",
387 "ctrl_link", 387 "ctrl_link",
388 "ctrl_link_iface", 388 "ctrl_link_iface",
389 "stream_pixel"; 389 "stream_pixel";
390 assigned-clocks = <&dispcc DISP_CC 390 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
391 <&dispcc DISP_CC 391 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
392 assigned-clock-parents = <&dp_phy 392 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
393 phys = <&dp_phy>; 393 phys = <&dp_phy>;
394 phy-names = "dp"; 394 phy-names = "dp";
395 395
396 operating-points-v2 = <&dp_opp_tab 396 operating-points-v2 = <&dp_opp_table>;
397 power-domains = <&rpmhpd SC7280_CX 397 power-domains = <&rpmhpd SC7280_CX>;
398 398
399 #sound-dai-cells = <0>; 399 #sound-dai-cells = <0>;
400 400
401 ports { 401 ports {
402 #address-cells = <1>; 402 #address-cells = <1>;
403 #size-cells = <0>; 403 #size-cells = <0>;
404 404
405 port@0 { 405 port@0 {
406 reg = <0>; 406 reg = <0>;
407 dp_in: endpoint { 407 dp_in: endpoint {
408 remote-endpoint = <&dp 408 remote-endpoint = <&dpu_intf0_out>;
409 }; 409 };
410 }; 410 };
411 411
412 port@1 { 412 port@1 {
413 reg = <1>; 413 reg = <1>;
414 dp_out: endpoint { }; 414 dp_out: endpoint { };
415 }; 415 };
416 }; 416 };
417 417
418 dp_opp_table: opp-table { 418 dp_opp_table: opp-table {
419 compatible = "operating-points 419 compatible = "operating-points-v2";
420 420
421 opp-160000000 { 421 opp-160000000 {
422 opp-hz = /bits/ 64 <160000 422 opp-hz = /bits/ 64 <160000000>;
423 required-opps = <&rpmhpd_o 423 required-opps = <&rpmhpd_opp_low_svs>;
424 }; 424 };
425 425
426 opp-270000000 { 426 opp-270000000 {
427 opp-hz = /bits/ 64 <270000 427 opp-hz = /bits/ 64 <270000000>;
428 required-opps = <&rpmhpd_o 428 required-opps = <&rpmhpd_opp_svs>;
429 }; 429 };
430 430
431 opp-540000000 { 431 opp-540000000 {
432 opp-hz = /bits/ 64 <540000 432 opp-hz = /bits/ 64 <540000000>;
433 required-opps = <&rpmhpd_o 433 required-opps = <&rpmhpd_opp_svs_l1>;
434 }; 434 };
435 435
436 opp-810000000 { 436 opp-810000000 {
437 opp-hz = /bits/ 64 <810000 437 opp-hz = /bits/ 64 <810000000>;
438 required-opps = <&rpmhpd_o 438 required-opps = <&rpmhpd_opp_nom>;
439 }; 439 };
440 }; 440 };
441 }; 441 };
442 }; 442 };
443 ... 443 ...
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