1 # SPDX-License-Identifier: GPL-2.0-only OR BSD 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/display/msm 4 $id: http://devicetree.org/schemas/display/msm/qcom,sdm845-dpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Qualcomm Display DPU on SDM845 7 title: Qualcomm Display DPU on SDM845
8 8
9 maintainers: 9 maintainers:
10 - Krishna Manikandan <quic_mkrishn@quicinc.co 10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
11 11
12 $ref: /schemas/display/msm/dpu-common.yaml# 12 $ref: /schemas/display/msm/dpu-common.yaml#
13 13
14 properties: 14 properties:
15 compatible: 15 compatible:
16 enum: 16 enum:
17 - qcom,sdm670-dpu 17 - qcom,sdm670-dpu
18 - qcom,sdm845-dpu 18 - qcom,sdm845-dpu
19 19
20 reg: 20 reg:
21 items: 21 items:
22 - description: Address offset and size f 22 - description: Address offset and size for mdp register set
23 - description: Address offset and size f 23 - description: Address offset and size for vbif register set
24 24
25 reg-names: 25 reg-names:
26 items: 26 items:
27 - const: mdp 27 - const: mdp
28 - const: vbif 28 - const: vbif
29 29
30 clocks: 30 clocks:
31 items: 31 items:
32 - description: Display GCC bus clock 32 - description: Display GCC bus clock
33 - description: Display ahb clock 33 - description: Display ahb clock
34 - description: Display axi clock 34 - description: Display axi clock
35 - description: Display core clock 35 - description: Display core clock
36 - description: Display vsync clock 36 - description: Display vsync clock
37 37
38 clock-names: 38 clock-names:
39 items: 39 items:
40 - const: gcc-bus 40 - const: gcc-bus
41 - const: iface 41 - const: iface
42 - const: bus 42 - const: bus
43 - const: core 43 - const: core
44 - const: vsync 44 - const: vsync
45 45
46 required: 46 required:
47 - compatible 47 - compatible
48 - reg 48 - reg
49 - reg-names 49 - reg-names
50 - clocks 50 - clocks
51 - clock-names 51 - clock-names
52 52
53 unevaluatedProperties: false 53 unevaluatedProperties: false
54 54
55 examples: 55 examples:
56 - | 56 - |
57 #include <dt-bindings/clock/qcom,dispcc-sd 57 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
58 #include <dt-bindings/clock/qcom,gcc-sdm84 58 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
59 #include <dt-bindings/power/qcom-rpmpd.h> 59 #include <dt-bindings/power/qcom-rpmpd.h>
60 60
61 display-controller@ae01000 { 61 display-controller@ae01000 {
62 compatible = "qcom,sdm845-dpu"; 62 compatible = "qcom,sdm845-dpu";
63 reg = <0x0ae01000 0x8f000>, 63 reg = <0x0ae01000 0x8f000>,
64 <0x0aeb0000 0x2008>; 64 <0x0aeb0000 0x2008>;
65 reg-names = "mdp", "vbif"; 65 reg-names = "mdp", "vbif";
66 66
67 clocks = <&gcc GCC_DISP_AXI_CLK>, 67 clocks = <&gcc GCC_DISP_AXI_CLK>,
68 <&dispcc DISP_CC_MDSS_AHB_CLK 68 <&dispcc DISP_CC_MDSS_AHB_CLK>,
69 <&dispcc DISP_CC_MDSS_AXI_CLK 69 <&dispcc DISP_CC_MDSS_AXI_CLK>,
70 <&dispcc DISP_CC_MDSS_MDP_CLK 70 <&dispcc DISP_CC_MDSS_MDP_CLK>,
71 <&dispcc DISP_CC_MDSS_VSYNC_C 71 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
72 clock-names = "gcc-bus", "iface", "bus 72 clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
73 73
74 interrupt-parent = <&mdss>; 74 interrupt-parent = <&mdss>;
75 interrupts = <0>; 75 interrupts = <0>;
76 power-domains = <&rpmhpd SDM845_CX>; 76 power-domains = <&rpmhpd SDM845_CX>;
77 operating-points-v2 = <&mdp_opp_table> 77 operating-points-v2 = <&mdp_opp_table>;
78 78
79 ports { 79 ports {
80 #address-cells = <1>; 80 #address-cells = <1>;
81 #size-cells = <0>; 81 #size-cells = <0>;
82 82
83 port@0 { 83 port@0 {
84 reg = <0>; 84 reg = <0>;
85 endpoint { 85 endpoint {
86 remote-endpoint = <&dsi0_i 86 remote-endpoint = <&dsi0_in>;
87 }; 87 };
88 }; 88 };
89 89
90 port@1 { 90 port@1 {
91 reg = <1>; 91 reg = <1>;
92 endpoint { 92 endpoint {
93 remote-endpoint = <&dsi1_i 93 remote-endpoint = <&dsi1_in>;
94 }; 94 };
95 }; 95 };
96 }; 96 };
97 }; 97 };
98 ... 98 ...
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