1 # SPDX-License-Identifier: GPL-2.0-only OR BSD 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/display/msm 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6375-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Qualcomm SM6375 Display MDSS 7 title: Qualcomm SM6375 Display MDSS
8 8
9 maintainers: 9 maintainers:
10 - Konrad Dybcio <konradybcio@kernel.org> 10 - Konrad Dybcio <konradybcio@kernel.org>
11 11
12 description: 12 description:
13 SM6375 MSM Mobile Display Subsystem (MDSS), 13 SM6375 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
14 like DPU display controller, DSI and DP inte 14 like DPU display controller, DSI and DP interfaces etc.
15 15
16 $ref: /schemas/display/msm/mdss-common.yaml# 16 $ref: /schemas/display/msm/mdss-common.yaml#
17 17
18 properties: 18 properties:
19 compatible: 19 compatible:
20 const: qcom,sm6375-mdss 20 const: qcom,sm6375-mdss
21 21
22 clocks: 22 clocks:
23 items: 23 items:
24 - description: Display AHB clock from gc 24 - description: Display AHB clock from gcc
25 - description: Display AHB clock 25 - description: Display AHB clock
26 - description: Display core clock 26 - description: Display core clock
27 27
28 clock-names: 28 clock-names:
29 items: 29 items:
30 - const: iface 30 - const: iface
31 - const: ahb 31 - const: ahb
32 - const: core 32 - const: core
33 33
34 iommus: 34 iommus:
35 maxItems: 1 35 maxItems: 1
36 36
37 interconnects: 37 interconnects:
38 items: 38 items:
39 - description: Interconnect path from md 39 - description: Interconnect path from mdp0 port to the data bus
40 - description: Interconnect path from CP 40 - description: Interconnect path from CPU to the reg bus
41 41
42 interconnect-names: 42 interconnect-names:
43 items: 43 items:
44 - const: mdp0-mem 44 - const: mdp0-mem
45 - const: cpu-cfg 45 - const: cpu-cfg
46 46
47 patternProperties: 47 patternProperties:
48 "^display-controller@[0-9a-f]+$": 48 "^display-controller@[0-9a-f]+$":
49 type: object 49 type: object
50 additionalProperties: true 50 additionalProperties: true
51 51
52 properties: 52 properties:
53 compatible: 53 compatible:
54 const: qcom,sm6375-dpu 54 const: qcom,sm6375-dpu
55 55
56 "^dsi@[0-9a-f]+$": 56 "^dsi@[0-9a-f]+$":
57 type: object 57 type: object
58 additionalProperties: true 58 additionalProperties: true
59 59
60 properties: 60 properties:
61 compatible: 61 compatible:
62 items: 62 items:
63 - const: qcom,sm6375-dsi-ctrl 63 - const: qcom,sm6375-dsi-ctrl
64 - const: qcom,mdss-dsi-ctrl 64 - const: qcom,mdss-dsi-ctrl
65 65
66 "^phy@[0-9a-f]+$": 66 "^phy@[0-9a-f]+$":
67 type: object 67 type: object
68 additionalProperties: true 68 additionalProperties: true
69 69
70 properties: 70 properties:
71 compatible: 71 compatible:
72 const: qcom,sm6375-dsi-phy-7nm 72 const: qcom,sm6375-dsi-phy-7nm
73 73
74 unevaluatedProperties: false 74 unevaluatedProperties: false
75 75
76 examples: 76 examples:
77 - | 77 - |
78 #include <dt-bindings/clock/qcom,rpmcc.h> 78 #include <dt-bindings/clock/qcom,rpmcc.h>
79 #include <dt-bindings/clock/qcom,sm6375-gc 79 #include <dt-bindings/clock/qcom,sm6375-gcc.h>
80 #include <dt-bindings/clock/qcom,sm6375-di 80 #include <dt-bindings/clock/qcom,sm6375-dispcc.h>
81 #include <dt-bindings/interrupt-controller 81 #include <dt-bindings/interrupt-controller/arm-gic.h>
82 #include <dt-bindings/power/qcom-rpmpd.h> 82 #include <dt-bindings/power/qcom-rpmpd.h>
83 83
84 display-subsystem@5e00000 { 84 display-subsystem@5e00000 {
85 compatible = "qcom,sm6375-mdss"; 85 compatible = "qcom,sm6375-mdss";
86 reg = <0x05e00000 0x1000>; 86 reg = <0x05e00000 0x1000>;
87 reg-names = "mdss"; 87 reg-names = "mdss";
88 88
89 power-domains = <&dispcc MDSS_GDSC>; 89 power-domains = <&dispcc MDSS_GDSC>;
90 90
91 clocks = <&gcc GCC_DISP_AHB_CLK>, 91 clocks = <&gcc GCC_DISP_AHB_CLK>,
92 <&dispcc DISP_CC_MDSS_AHB_CLK 92 <&dispcc DISP_CC_MDSS_AHB_CLK>,
93 <&dispcc DISP_CC_MDSS_MDP_CLK 93 <&dispcc DISP_CC_MDSS_MDP_CLK>;
94 clock-names = "iface", "ahb", "core"; 94 clock-names = "iface", "ahb", "core";
95 95
96 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVE 96 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
97 interrupt-controller; 97 interrupt-controller;
98 #interrupt-cells = <1>; 98 #interrupt-cells = <1>;
99 99
100 iommus = <&apps_smmu 0x820 0x2>; 100 iommus = <&apps_smmu 0x820 0x2>;
101 #address-cells = <1>; 101 #address-cells = <1>;
102 #size-cells = <1>; 102 #size-cells = <1>;
103 ranges; 103 ranges;
104 104
105 display-controller@5e01000 { 105 display-controller@5e01000 {
106 compatible = "qcom,sm6375-dpu"; 106 compatible = "qcom,sm6375-dpu";
107 reg = <0x05e01000 0x8e030>, 107 reg = <0x05e01000 0x8e030>,
108 <0x05eb0000 0x2008>; 108 <0x05eb0000 0x2008>;
109 reg-names = "mdp", "vbif"; 109 reg-names = "mdp", "vbif";
110 110
111 clocks = <&gcc GCC_DISP_HF_AXI_CLK 111 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
112 <&dispcc DISP_CC_MDSS_AHB 112 <&dispcc DISP_CC_MDSS_AHB_CLK>,
113 <&dispcc DISP_CC_MDSS_ROT 113 <&dispcc DISP_CC_MDSS_ROT_CLK>,
114 <&dispcc DISP_CC_MDSS_MDP 114 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
115 <&dispcc DISP_CC_MDSS_MDP 115 <&dispcc DISP_CC_MDSS_MDP_CLK>,
116 <&dispcc DISP_CC_MDSS_VSY 116 <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
117 <&gcc GCC_DISP_THROTTLE_C 117 <&gcc GCC_DISP_THROTTLE_CORE_CLK>;
118 clock-names = "bus", 118 clock-names = "bus",
119 "iface", 119 "iface",
120 "rot", 120 "rot",
121 "lut", 121 "lut",
122 "core", 122 "core",
123 "vsync", 123 "vsync",
124 "throttle"; 124 "throttle";
125 125
126 assigned-clocks = <&dispcc DISP_CC 126 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
127 assigned-clock-rates = <19200000>; 127 assigned-clock-rates = <19200000>;
128 128
129 operating-points-v2 = <&mdp_opp_ta 129 operating-points-v2 = <&mdp_opp_table>;
130 power-domains = <&rpmpd SM6375_VDD 130 power-domains = <&rpmpd SM6375_VDDCX>;
131 131
132 interrupt-parent = <&mdss>; 132 interrupt-parent = <&mdss>;
133 interrupts = <0>; 133 interrupts = <0>;
134 134
135 ports { 135 ports {
136 #address-cells = <1>; 136 #address-cells = <1>;
137 #size-cells = <0>; 137 #size-cells = <0>;
138 138
139 port@0 { 139 port@0 {
140 reg = <0>; 140 reg = <0>;
141 dpu_intf1_out: endpoint { 141 dpu_intf1_out: endpoint {
142 remote-endpoint = <&ds 142 remote-endpoint = <&dsi0_in>;
143 }; 143 };
144 }; 144 };
145 }; 145 };
146 }; 146 };
147 147
148 dsi@5e94000 { 148 dsi@5e94000 {
149 compatible = "qcom,sm6375-dsi-ctrl 149 compatible = "qcom,sm6375-dsi-ctrl", "qcom,mdss-dsi-ctrl";
150 reg = <0x05e94000 0x400>; 150 reg = <0x05e94000 0x400>;
151 reg-names = "dsi_ctrl"; 151 reg-names = "dsi_ctrl";
152 152
153 interrupt-parent = <&mdss>; 153 interrupt-parent = <&mdss>;
154 interrupts = <4>; 154 interrupts = <4>;
155 155
156 clocks = <&dispcc DISP_CC_MDSS_BYT 156 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
157 <&dispcc DISP_CC_MDSS_BYT 157 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
158 <&dispcc DISP_CC_MDSS_PCL 158 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
159 <&dispcc DISP_CC_MDSS_ESC 159 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
160 <&dispcc DISP_CC_MDSS_AHB 160 <&dispcc DISP_CC_MDSS_AHB_CLK>,
161 <&gcc GCC_DISP_HF_AXI_CLK 161 <&gcc GCC_DISP_HF_AXI_CLK>;
162 clock-names = "byte", 162 clock-names = "byte",
163 "byte_intf", 163 "byte_intf",
164 "pixel", 164 "pixel",
165 "core", 165 "core",
166 "iface", 166 "iface",
167 "bus"; 167 "bus";
168 168
169 assigned-clocks = <&dispcc DISP_CC 169 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
170 <&dispcc DISP_CC 170 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
171 assigned-clock-parents = <&mdss_ds 171 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
172 172
173 operating-points-v2 = <&dsi_opp_ta 173 operating-points-v2 = <&dsi_opp_table>;
174 power-domains = <&rpmpd SM6375_VDD 174 power-domains = <&rpmpd SM6375_VDDMX>;
175 175
176 phys = <&mdss_dsi0_phy>; 176 phys = <&mdss_dsi0_phy>;
177 phy-names = "dsi"; 177 phy-names = "dsi";
178 178
179 #address-cells = <1>; 179 #address-cells = <1>;
180 #size-cells = <0>; 180 #size-cells = <0>;
181 181
182 ports { 182 ports {
183 #address-cells = <1>; 183 #address-cells = <1>;
184 #size-cells = <0>; 184 #size-cells = <0>;
185 185
186 port@0 { 186 port@0 {
187 reg = <0>; 187 reg = <0>;
188 dsi0_in: endpoint { 188 dsi0_in: endpoint {
189 remote-endpoint = <&dp 189 remote-endpoint = <&dpu_intf1_out>;
190 }; 190 };
191 }; 191 };
192 192
193 port@1 { 193 port@1 {
194 reg = <1>; 194 reg = <1>;
195 dsi0_out: endpoint { 195 dsi0_out: endpoint {
196 }; 196 };
197 }; 197 };
198 }; 198 };
199 }; 199 };
200 200
201 mdss_dsi0_phy: phy@5e94400 { 201 mdss_dsi0_phy: phy@5e94400 {
202 compatible = "qcom,sm6375-dsi-phy- 202 compatible = "qcom,sm6375-dsi-phy-7nm";
203 reg = <0x05e94400 0x200>, 203 reg = <0x05e94400 0x200>,
204 <0x05e94600 0x280>, 204 <0x05e94600 0x280>,
205 <0x05e94900 0x264>; 205 <0x05e94900 0x264>;
206 reg-names = "dsi_phy", 206 reg-names = "dsi_phy",
207 "dsi_phy_lane", 207 "dsi_phy_lane",
208 "dsi_pll"; 208 "dsi_pll";
209 209
210 #clock-cells = <1>; 210 #clock-cells = <1>;
211 #phy-cells = <0>; 211 #phy-cells = <0>;
212 212
213 clocks = <&dispcc DISP_CC_MDSS_AHB 213 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
214 <&rpmcc RPM_SMD_XO_CLK_SR 214 <&rpmcc RPM_SMD_XO_CLK_SRC>;
215 clock-names = "iface", "ref"; 215 clock-names = "iface", "ref";
216 }; 216 };
217 }; 217 };
218 ... 218 ...
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