1 # SPDX-License-Identifier: GPL-2.0-only OR BSD 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/display/msm 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8350-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Qualcomm SM8350 Display MDSS 7 title: Qualcomm SM8350 Display MDSS
8 8
9 maintainers: 9 maintainers:
10 - Robert Foss <robert.foss@linaro.org> 10 - Robert Foss <robert.foss@linaro.org>
11 11
12 description: 12 description:
13 MSM Mobile Display Subsystem(MDSS) that enca 13 MSM Mobile Display Subsystem(MDSS) that encapsulates sub-blocks like
14 DPU display controller, DSI and DP interface 14 DPU display controller, DSI and DP interfaces etc.
15 15
16 $ref: /schemas/display/msm/mdss-common.yaml# 16 $ref: /schemas/display/msm/mdss-common.yaml#
17 17
18 properties: 18 properties:
19 compatible: 19 compatible:
20 items: 20 items:
21 - const: qcom,sm8350-mdss 21 - const: qcom,sm8350-mdss
22 22
23 clocks: 23 clocks:
24 items: 24 items:
25 - description: Display AHB clock from gc 25 - description: Display AHB clock from gcc
26 - description: Display hf axi clock 26 - description: Display hf axi clock
27 - description: Display sf axi clock 27 - description: Display sf axi clock
28 - description: Display core clock 28 - description: Display core clock
29 29
30 clock-names: 30 clock-names:
31 items: 31 items:
32 - const: iface 32 - const: iface
33 - const: bus 33 - const: bus
34 - const: nrt_bus 34 - const: nrt_bus
35 - const: core 35 - const: core
36 36
37 iommus: 37 iommus:
38 maxItems: 1 38 maxItems: 1
39 39
40 interconnects: 40 interconnects:
41 maxItems: 2 41 maxItems: 2
42 42
43 interconnect-names: 43 interconnect-names:
44 items: 44 items:
45 - const: mdp0-mem 45 - const: mdp0-mem
46 - const: mdp1-mem 46 - const: mdp1-mem
47 47
48 patternProperties: 48 patternProperties:
49 "^display-controller@[0-9a-f]+$": 49 "^display-controller@[0-9a-f]+$":
50 type: object 50 type: object
51 additionalProperties: true 51 additionalProperties: true
52 52
53 properties: 53 properties:
54 compatible: 54 compatible:
55 const: qcom,sm8350-dpu 55 const: qcom,sm8350-dpu
56 56
57 "^displayport-controller@[0-9a-f]+$": 57 "^displayport-controller@[0-9a-f]+$":
58 type: object 58 type: object
59 additionalProperties: true 59 additionalProperties: true
60 60
61 properties: 61 properties:
62 compatible: 62 compatible:
63 const: qcom,sm8350-dp 63 const: qcom,sm8350-dp
64 64
65 "^dsi@[0-9a-f]+$": 65 "^dsi@[0-9a-f]+$":
66 type: object 66 type: object
67 additionalProperties: true 67 additionalProperties: true
68 68
69 properties: 69 properties:
70 compatible: 70 compatible:
71 items: 71 items:
72 - const: qcom,sm8350-dsi-ctrl 72 - const: qcom,sm8350-dsi-ctrl
73 - const: qcom,mdss-dsi-ctrl 73 - const: qcom,mdss-dsi-ctrl
74 74
75 "^phy@[0-9a-f]+$": 75 "^phy@[0-9a-f]+$":
76 type: object 76 type: object
77 additionalProperties: true 77 additionalProperties: true
78 78
79 properties: 79 properties:
80 compatible: 80 compatible:
81 const: qcom,sm8350-dsi-phy-5nm 81 const: qcom,sm8350-dsi-phy-5nm
82 82
83 unevaluatedProperties: false 83 unevaluatedProperties: false
84 84
85 examples: 85 examples:
86 - | 86 - |
87 #include <dt-bindings/clock/qcom,dispcc-sm 87 #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
88 #include <dt-bindings/clock/qcom,gcc-sm835 88 #include <dt-bindings/clock/qcom,gcc-sm8350.h>
89 #include <dt-bindings/clock/qcom,rpmh.h> 89 #include <dt-bindings/clock/qcom,rpmh.h>
90 #include <dt-bindings/interrupt-controller 90 #include <dt-bindings/interrupt-controller/arm-gic.h>
91 #include <dt-bindings/interconnect/qcom,sm 91 #include <dt-bindings/interconnect/qcom,sm8350.h>
92 #include <dt-bindings/power/qcom,rpmhpd.h> 92 #include <dt-bindings/power/qcom,rpmhpd.h>
93 93
94 display-subsystem@ae00000 { 94 display-subsystem@ae00000 {
95 compatible = "qcom,sm8350-mdss"; 95 compatible = "qcom,sm8350-mdss";
96 reg = <0x0ae00000 0x1000>; 96 reg = <0x0ae00000 0x1000>;
97 reg-names = "mdss"; 97 reg-names = "mdss";
98 98
99 interconnects = <&mmss_noc MASTER_MDP0 99 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
100 <&mmss_noc MASTER_MDP1 100 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
101 interconnect-names = "mdp0-mem", "mdp1 101 interconnect-names = "mdp0-mem", "mdp1-mem";
102 102
103 power-domains = <&dispcc MDSS_GDSC>; 103 power-domains = <&dispcc MDSS_GDSC>;
104 resets = <&dispcc DISP_CC_MDSS_CORE_BC 104 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
105 105
106 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK 106 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
107 <&gcc GCC_DISP_HF_AXI_CLK>, 107 <&gcc GCC_DISP_HF_AXI_CLK>,
108 <&gcc GCC_DISP_SF_AXI_CLK>, 108 <&gcc GCC_DISP_SF_AXI_CLK>,
109 <&dispcc DISP_CC_MDSS_MDP_CLK 109 <&dispcc DISP_CC_MDSS_MDP_CLK>;
110 clock-names = "iface", "bus", "nrt_bus 110 clock-names = "iface", "bus", "nrt_bus", "core";
111 111
112 iommus = <&apps_smmu 0x820 0x402>; 112 iommus = <&apps_smmu 0x820 0x402>;
113 113
114 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVE 114 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
115 interrupt-controller; 115 interrupt-controller;
116 #interrupt-cells = <1>; 116 #interrupt-cells = <1>;
117 117
118 #address-cells = <1>; 118 #address-cells = <1>;
119 #size-cells = <1>; 119 #size-cells = <1>;
120 ranges; 120 ranges;
121 121
122 display-controller@ae01000 { 122 display-controller@ae01000 {
123 compatible = "qcom,sm8350-dpu"; 123 compatible = "qcom,sm8350-dpu";
124 reg = <0x0ae01000 0x8f000>, 124 reg = <0x0ae01000 0x8f000>,
125 <0x0aeb0000 0x2008>; 125 <0x0aeb0000 0x2008>;
126 reg-names = "mdp", "vbif"; 126 reg-names = "mdp", "vbif";
127 127
128 clocks = <&gcc GCC_DISP_HF_AXI_CLK 128 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
129 <&gcc GCC_DISP_SF_AXI_CLK 129 <&gcc GCC_DISP_SF_AXI_CLK>,
130 <&dispcc DISP_CC_MDSS_AHB 130 <&dispcc DISP_CC_MDSS_AHB_CLK>,
131 <&dispcc DISP_CC_MDSS_MDP 131 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
132 <&dispcc DISP_CC_MDSS_MDP 132 <&dispcc DISP_CC_MDSS_MDP_CLK>,
133 <&dispcc DISP_CC_MDSS_VSY 133 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
134 clock-names = "bus", 134 clock-names = "bus",
135 "nrt_bus", 135 "nrt_bus",
136 "iface", 136 "iface",
137 "lut", 137 "lut",
138 "core", 138 "core",
139 "vsync"; 139 "vsync";
140 140
141 assigned-clocks = <&dispcc DISP_CC 141 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
142 assigned-clock-rates = <19200000>; 142 assigned-clock-rates = <19200000>;
143 143
144 operating-points-v2 = <&mdp_opp_ta 144 operating-points-v2 = <&mdp_opp_table>;
145 power-domains = <&rpmhpd RPMHPD_MM 145 power-domains = <&rpmhpd RPMHPD_MMCX>;
146 146
147 interrupt-parent = <&mdss>; 147 interrupt-parent = <&mdss>;
148 interrupts = <0>; 148 interrupts = <0>;
149 149
150 ports { 150 ports {
151 #address-cells = <1>; 151 #address-cells = <1>;
152 #size-cells = <0>; 152 #size-cells = <0>;
153 153
154 port@0 { 154 port@0 {
155 reg = <0>; 155 reg = <0>;
156 dpu_intf1_out: endpoint { 156 dpu_intf1_out: endpoint {
157 remote-endpoint = <&ds 157 remote-endpoint = <&dsi0_in>;
158 }; 158 };
159 }; 159 };
160 }; 160 };
161 161
162 mdp_opp_table: opp-table { 162 mdp_opp_table: opp-table {
163 compatible = "operating-points 163 compatible = "operating-points-v2";
164 164
165 opp-200000000 { 165 opp-200000000 {
166 opp-hz = /bits/ 64 <200000 166 opp-hz = /bits/ 64 <200000000>;
167 required-opps = <&rpmhpd_o 167 required-opps = <&rpmhpd_opp_low_svs>;
168 }; 168 };
169 169
170 opp-300000000 { 170 opp-300000000 {
171 opp-hz = /bits/ 64 <300000 171 opp-hz = /bits/ 64 <300000000>;
172 required-opps = <&rpmhpd_o 172 required-opps = <&rpmhpd_opp_svs>;
173 }; 173 };
174 174
175 opp-345000000 { 175 opp-345000000 {
176 opp-hz = /bits/ 64 <345000 176 opp-hz = /bits/ 64 <345000000>;
177 required-opps = <&rpmhpd_o 177 required-opps = <&rpmhpd_opp_svs_l1>;
178 }; 178 };
179 179
180 opp-460000000 { 180 opp-460000000 {
181 opp-hz = /bits/ 64 <460000 181 opp-hz = /bits/ 64 <460000000>;
182 required-opps = <&rpmhpd_o 182 required-opps = <&rpmhpd_opp_nom>;
183 }; 183 };
184 }; 184 };
185 }; 185 };
186 186
187 dsi0: dsi@ae94000 { 187 dsi0: dsi@ae94000 {
188 compatible = "qcom,sm8350-dsi-ctrl 188 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
189 reg = <0x0ae94000 0x400>; 189 reg = <0x0ae94000 0x400>;
190 reg-names = "dsi_ctrl"; 190 reg-names = "dsi_ctrl";
191 191
192 interrupt-parent = <&mdss>; 192 interrupt-parent = <&mdss>;
193 interrupts = <4>; 193 interrupts = <4>;
194 194
195 clocks = <&dispcc DISP_CC_MDSS_BYT 195 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
196 <&dispcc DISP_CC_MDSS_BYT 196 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
197 <&dispcc DISP_CC_MDSS_PCL 197 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
198 <&dispcc DISP_CC_MDSS_ESC 198 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
199 <&dispcc DISP_CC_MDSS_AHB 199 <&dispcc DISP_CC_MDSS_AHB_CLK>,
200 <&gcc GCC_DISP_HF_AXI_CLK 200 <&gcc GCC_DISP_HF_AXI_CLK>;
201 clock-names = "byte", 201 clock-names = "byte",
202 "byte_intf", 202 "byte_intf",
203 "pixel", 203 "pixel",
204 "core", 204 "core",
205 "iface", 205 "iface",
206 "bus"; 206 "bus";
207 207
208 assigned-clocks = <&dispcc DISP_CC 208 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
209 <&dispcc DISP_CC_MDS 209 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
210 assigned-clock-parents = <&mdss_ds 210 assigned-clock-parents = <&mdss_dsi0_phy 0>,
211 <&mdss_dsi0_p 211 <&mdss_dsi0_phy 1>;
212 212
213 operating-points-v2 = <&dsi_opp_ta 213 operating-points-v2 = <&dsi_opp_table>;
214 power-domains = <&rpmhpd RPMHPD_MM 214 power-domains = <&rpmhpd RPMHPD_MMCX>;
215 215
216 phys = <&mdss_dsi0_phy>; 216 phys = <&mdss_dsi0_phy>;
217 217
218 ports { 218 ports {
219 #address-cells = <1>; 219 #address-cells = <1>;
220 #size-cells = <0>; 220 #size-cells = <0>;
221 221
222 port@0 { 222 port@0 {
223 reg = <0>; 223 reg = <0>;
224 dsi0_in: endpoint { 224 dsi0_in: endpoint {
225 remote-endpoint = <&dp 225 remote-endpoint = <&dpu_intf1_out>;
226 }; 226 };
227 }; 227 };
228 228
229 port@1 { 229 port@1 {
230 reg = <1>; 230 reg = <1>;
231 dsi0_out: endpoint { 231 dsi0_out: endpoint {
232 }; 232 };
233 }; 233 };
234 }; 234 };
235 }; 235 };
236 }; 236 };
237 ... 237 ...
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