1 # SPDX-License-Identifier: GPL-2.0-only OR BSD 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/display/msm 4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8650-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Qualcomm SM8650 Display MDSS 7 title: Qualcomm SM8650 Display MDSS
8 8
9 maintainers: 9 maintainers:
10 - Neil Armstrong <neil.armstrong@linaro.org> 10 - Neil Armstrong <neil.armstrong@linaro.org>
11 11
12 description: 12 description:
13 SM8650 MSM Mobile Display Subsystem(MDSS), w 13 SM8650 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14 DPU display controller, DSI and DP interface 14 DPU display controller, DSI and DP interfaces etc.
15 15
16 $ref: /schemas/display/msm/mdss-common.yaml# 16 $ref: /schemas/display/msm/mdss-common.yaml#
17 17
18 properties: 18 properties:
19 compatible: 19 compatible:
20 const: qcom,sm8650-mdss 20 const: qcom,sm8650-mdss
21 21
22 clocks: 22 clocks:
23 items: 23 items:
24 - description: Display AHB 24 - description: Display AHB
25 - description: Display hf AXI 25 - description: Display hf AXI
26 - description: Display core 26 - description: Display core
27 27
28 iommus: 28 iommus:
29 maxItems: 1 29 maxItems: 1
30 30
31 interconnects: 31 interconnects:
32 maxItems: 2 32 maxItems: 2
33 33
34 interconnect-names: 34 interconnect-names:
35 maxItems: 2 35 maxItems: 2
36 36
37 patternProperties: 37 patternProperties:
38 "^display-controller@[0-9a-f]+$": 38 "^display-controller@[0-9a-f]+$":
39 type: object 39 type: object
40 additionalProperties: true 40 additionalProperties: true
41 properties: 41 properties:
42 compatible: 42 compatible:
43 const: qcom,sm8650-dpu 43 const: qcom,sm8650-dpu
44 44
45 "^displayport-controller@[0-9a-f]+$": 45 "^displayport-controller@[0-9a-f]+$":
46 type: object 46 type: object
47 additionalProperties: true 47 additionalProperties: true
48 properties: 48 properties:
49 compatible: 49 compatible:
50 const: qcom,sm8650-dp 50 const: qcom,sm8650-dp
51 51
52 "^dsi@[0-9a-f]+$": 52 "^dsi@[0-9a-f]+$":
53 type: object 53 type: object
54 additionalProperties: true 54 additionalProperties: true
55 properties: 55 properties:
56 compatible: 56 compatible:
57 items: 57 items:
58 - const: qcom,sm8650-dsi-ctrl 58 - const: qcom,sm8650-dsi-ctrl
59 - const: qcom,mdss-dsi-ctrl 59 - const: qcom,mdss-dsi-ctrl
60 60
61 "^phy@[0-9a-f]+$": 61 "^phy@[0-9a-f]+$":
62 type: object 62 type: object
63 additionalProperties: true 63 additionalProperties: true
64 properties: 64 properties:
65 compatible: 65 compatible:
66 const: qcom,sm8650-dsi-phy-4nm 66 const: qcom,sm8650-dsi-phy-4nm
67 67
68 required: 68 required:
69 - compatible 69 - compatible
70 70
71 unevaluatedProperties: false 71 unevaluatedProperties: false
72 72
73 examples: 73 examples:
74 - | 74 - |
75 #include <dt-bindings/clock/qcom,rpmh.h> 75 #include <dt-bindings/clock/qcom,rpmh.h>
76 #include <dt-bindings/interrupt-controller 76 #include <dt-bindings/interrupt-controller/arm-gic.h>
77 #include <dt-bindings/power/qcom,rpmhpd.h> 77 #include <dt-bindings/power/qcom,rpmhpd.h>
78 78
79 display-subsystem@ae00000 { 79 display-subsystem@ae00000 {
80 compatible = "qcom,sm8650-mdss"; 80 compatible = "qcom,sm8650-mdss";
81 reg = <0x0ae00000 0x1000>; 81 reg = <0x0ae00000 0x1000>;
82 reg-names = "mdss"; 82 reg-names = "mdss";
83 83
84 resets = <&dispcc_core_bcr>; 84 resets = <&dispcc_core_bcr>;
85 85
86 power-domains = <&dispcc_gdsc>; 86 power-domains = <&dispcc_gdsc>;
87 87
88 clocks = <&gcc_ahb_clk>, 88 clocks = <&gcc_ahb_clk>,
89 <&gcc_axi_clk>, 89 <&gcc_axi_clk>,
90 <&dispcc_mdp_clk>; 90 <&dispcc_mdp_clk>;
91 clock-names = "bus", "nrt_bus", "core" 91 clock-names = "bus", "nrt_bus", "core";
92 92
93 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVE 93 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
94 interrupt-controller; 94 interrupt-controller;
95 #interrupt-cells = <1>; 95 #interrupt-cells = <1>;
96 96
97 iommus = <&apps_smmu 0x1c00 0x2>; 97 iommus = <&apps_smmu 0x1c00 0x2>;
98 98
99 #address-cells = <1>; 99 #address-cells = <1>;
100 #size-cells = <1>; 100 #size-cells = <1>;
101 ranges; 101 ranges;
102 102
103 display-controller@ae01000 { 103 display-controller@ae01000 {
104 compatible = "qcom,sm8650-dpu"; 104 compatible = "qcom,sm8650-dpu";
105 reg = <0x0ae01000 0x8f000>, 105 reg = <0x0ae01000 0x8f000>,
106 <0x0aeb0000 0x2008>; 106 <0x0aeb0000 0x2008>;
107 reg-names = "mdp", "vbif"; 107 reg-names = "mdp", "vbif";
108 108
109 clocks = <&gcc_axi_clk>, 109 clocks = <&gcc_axi_clk>,
110 <&dispcc_ahb_clk>, 110 <&dispcc_ahb_clk>,
111 <&dispcc_mdp_lut_clk>, 111 <&dispcc_mdp_lut_clk>,
112 <&dispcc_mdp_clk>, 112 <&dispcc_mdp_clk>,
113 <&dispcc_mdp_vsync_clk>; 113 <&dispcc_mdp_vsync_clk>;
114 clock-names = "nrt_bus", 114 clock-names = "nrt_bus",
115 "iface", 115 "iface",
116 "lut", 116 "lut",
117 "core", 117 "core",
118 "vsync"; 118 "vsync";
119 119
120 assigned-clocks = <&dispcc_mdp_vsy 120 assigned-clocks = <&dispcc_mdp_vsync_clk>;
121 assigned-clock-rates = <19200000>; 121 assigned-clock-rates = <19200000>;
122 122
123 operating-points-v2 = <&mdp_opp_ta 123 operating-points-v2 = <&mdp_opp_table>;
124 power-domains = <&rpmhpd RPMHPD_MM 124 power-domains = <&rpmhpd RPMHPD_MMCX>;
125 125
126 interrupt-parent = <&mdss>; 126 interrupt-parent = <&mdss>;
127 interrupts = <0>; 127 interrupts = <0>;
128 128
129 ports { 129 ports {
130 #address-cells = <1>; 130 #address-cells = <1>;
131 #size-cells = <0>; 131 #size-cells = <0>;
132 132
133 port@0 { 133 port@0 {
134 reg = <0>; 134 reg = <0>;
135 dpu_intf1_out: endpoint { 135 dpu_intf1_out: endpoint {
136 remote-endpoint = <&ds 136 remote-endpoint = <&dsi0_in>;
137 }; 137 };
138 }; 138 };
139 139
140 port@1 { 140 port@1 {
141 reg = <1>; 141 reg = <1>;
142 dpu_intf2_out: endpoint { 142 dpu_intf2_out: endpoint {
143 remote-endpoint = <&ds 143 remote-endpoint = <&dsi1_in>;
144 }; 144 };
145 }; 145 };
146 }; 146 };
147 147
148 mdp_opp_table: opp-table { 148 mdp_opp_table: opp-table {
149 compatible = "operating-points 149 compatible = "operating-points-v2";
150 150
151 opp-200000000 { 151 opp-200000000 {
152 opp-hz = /bits/ 64 <200000 152 opp-hz = /bits/ 64 <200000000>;
153 required-opps = <&rpmhpd_o 153 required-opps = <&rpmhpd_opp_low_svs>;
154 }; 154 };
155 155
156 opp-325000000 { 156 opp-325000000 {
157 opp-hz = /bits/ 64 <325000 157 opp-hz = /bits/ 64 <325000000>;
158 required-opps = <&rpmhpd_o 158 required-opps = <&rpmhpd_opp_svs>;
159 }; 159 };
160 160
161 opp-375000000 { 161 opp-375000000 {
162 opp-hz = /bits/ 64 <375000 162 opp-hz = /bits/ 64 <375000000>;
163 required-opps = <&rpmhpd_o 163 required-opps = <&rpmhpd_opp_svs_l1>;
164 }; 164 };
165 165
166 opp-514000000 { 166 opp-514000000 {
167 opp-hz = /bits/ 64 <514000 167 opp-hz = /bits/ 64 <514000000>;
168 required-opps = <&rpmhpd_o 168 required-opps = <&rpmhpd_opp_nom>;
169 }; 169 };
170 }; 170 };
171 }; 171 };
172 172
173 dsi@ae94000 { 173 dsi@ae94000 {
174 compatible = "qcom,sm8650-dsi-ctrl 174 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl";
175 reg = <0x0ae94000 0x400>; 175 reg = <0x0ae94000 0x400>;
176 reg-names = "dsi_ctrl"; 176 reg-names = "dsi_ctrl";
177 177
178 interrupt-parent = <&mdss>; 178 interrupt-parent = <&mdss>;
179 interrupts = <4>; 179 interrupts = <4>;
180 180
181 clocks = <&dispc_byte_clk>, 181 clocks = <&dispc_byte_clk>,
182 <&dispcc_intf_clk>, 182 <&dispcc_intf_clk>,
183 <&dispcc_pclk>, 183 <&dispcc_pclk>,
184 <&dispcc_esc_clk>, 184 <&dispcc_esc_clk>,
185 <&dispcc_ahb_clk>, 185 <&dispcc_ahb_clk>,
186 <&gcc_bus_clk>; 186 <&gcc_bus_clk>;
187 clock-names = "byte", 187 clock-names = "byte",
188 "byte_intf", 188 "byte_intf",
189 "pixel", 189 "pixel",
190 "core", 190 "core",
191 "iface", 191 "iface",
192 "bus"; 192 "bus";
193 193
194 assigned-clocks = <&dispcc_byte_cl 194 assigned-clocks = <&dispcc_byte_clk>,
195 <&dispcc_pclk>; 195 <&dispcc_pclk>;
196 assigned-clock-parents = <&dsi0_ph 196 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
197 197
198 operating-points-v2 = <&dsi_opp_ta 198 operating-points-v2 = <&dsi_opp_table>;
199 power-domains = <&rpmhpd RPMHPD_MM 199 power-domains = <&rpmhpd RPMHPD_MMCX>;
200 200
201 phys = <&dsi0_phy>; 201 phys = <&dsi0_phy>;
202 phy-names = "dsi"; 202 phy-names = "dsi";
203 203
204 #address-cells = <1>; 204 #address-cells = <1>;
205 #size-cells = <0>; 205 #size-cells = <0>;
206 206
207 ports { 207 ports {
208 #address-cells = <1>; 208 #address-cells = <1>;
209 #size-cells = <0>; 209 #size-cells = <0>;
210 210
211 port@0 { 211 port@0 {
212 reg = <0>; 212 reg = <0>;
213 dsi0_in: endpoint { 213 dsi0_in: endpoint {
214 remote-endpoint = <&dp 214 remote-endpoint = <&dpu_intf1_out>;
215 }; 215 };
216 }; 216 };
217 217
218 port@1 { 218 port@1 {
219 reg = <1>; 219 reg = <1>;
220 dsi0_out: endpoint { 220 dsi0_out: endpoint {
221 }; 221 };
222 }; 222 };
223 }; 223 };
224 224
225 dsi_opp_table: opp-table { 225 dsi_opp_table: opp-table {
226 compatible = "operating-points 226 compatible = "operating-points-v2";
227 227
228 opp-187500000 { 228 opp-187500000 {
229 opp-hz = /bits/ 64 <187500 229 opp-hz = /bits/ 64 <187500000>;
230 required-opps = <&rpmhpd_o 230 required-opps = <&rpmhpd_opp_low_svs>;
231 }; 231 };
232 232
233 opp-300000000 { 233 opp-300000000 {
234 opp-hz = /bits/ 64 <300000 234 opp-hz = /bits/ 64 <300000000>;
235 required-opps = <&rpmhpd_o 235 required-opps = <&rpmhpd_opp_svs>;
236 }; 236 };
237 237
238 opp-358000000 { 238 opp-358000000 {
239 opp-hz = /bits/ 64 <358000 239 opp-hz = /bits/ 64 <358000000>;
240 required-opps = <&rpmhpd_o 240 required-opps = <&rpmhpd_opp_svs_l1>;
241 }; 241 };
242 }; 242 };
243 }; 243 };
244 244
245 dsi0_phy: phy@ae94400 { 245 dsi0_phy: phy@ae94400 {
246 compatible = "qcom,sm8650-dsi-phy- 246 compatible = "qcom,sm8650-dsi-phy-4nm";
247 reg = <0x0ae95000 0x200>, 247 reg = <0x0ae95000 0x200>,
248 <0x0ae95200 0x280>, 248 <0x0ae95200 0x280>,
249 <0x0ae95500 0x400>; 249 <0x0ae95500 0x400>;
250 reg-names = "dsi_phy", 250 reg-names = "dsi_phy",
251 "dsi_phy_lane", 251 "dsi_phy_lane",
252 "dsi_pll"; 252 "dsi_pll";
253 253
254 #clock-cells = <1>; 254 #clock-cells = <1>;
255 #phy-cells = <0>; 255 #phy-cells = <0>;
256 256
257 clocks = <&dispcc_iface_clk>, 257 clocks = <&dispcc_iface_clk>,
258 <&rpmhcc_ref_clk>; 258 <&rpmhcc_ref_clk>;
259 clock-names = "iface", "ref"; 259 clock-names = "iface", "ref";
260 }; 260 };
261 261
262 dsi@ae96000 { 262 dsi@ae96000 {
263 compatible = "qcom,sm8650-dsi-ctrl 263 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl";
264 reg = <0x0ae96000 0x400>; 264 reg = <0x0ae96000 0x400>;
265 reg-names = "dsi_ctrl"; 265 reg-names = "dsi_ctrl";
266 266
267 interrupt-parent = <&mdss>; 267 interrupt-parent = <&mdss>;
268 interrupts = <5>; 268 interrupts = <5>;
269 269
270 clocks = <&dispc_byte_clk>, 270 clocks = <&dispc_byte_clk>,
271 <&dispcc_intf_clk>, 271 <&dispcc_intf_clk>,
272 <&dispcc_pclk>, 272 <&dispcc_pclk>,
273 <&dispcc_esc_clk>, 273 <&dispcc_esc_clk>,
274 <&dispcc_ahb_clk>, 274 <&dispcc_ahb_clk>,
275 <&gcc_bus_clk>; 275 <&gcc_bus_clk>;
276 clock-names = "byte", 276 clock-names = "byte",
277 "byte_intf", 277 "byte_intf",
278 "pixel", 278 "pixel",
279 "core", 279 "core",
280 "iface", 280 "iface",
281 "bus"; 281 "bus";
282 282
283 assigned-clocks = <&dispcc_byte_cl 283 assigned-clocks = <&dispcc_byte_clk>,
284 <&dispcc_pclk>; 284 <&dispcc_pclk>;
285 assigned-clock-parents = <&dsi1_ph 285 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
286 286
287 operating-points-v2 = <&dsi_opp_ta 287 operating-points-v2 = <&dsi_opp_table>;
288 power-domains = <&rpmhpd RPMHPD_MM 288 power-domains = <&rpmhpd RPMHPD_MMCX>;
289 289
290 phys = <&dsi1_phy>; 290 phys = <&dsi1_phy>;
291 phy-names = "dsi"; 291 phy-names = "dsi";
292 292
293 #address-cells = <1>; 293 #address-cells = <1>;
294 #size-cells = <0>; 294 #size-cells = <0>;
295 295
296 ports { 296 ports {
297 #address-cells = <1>; 297 #address-cells = <1>;
298 #size-cells = <0>; 298 #size-cells = <0>;
299 299
300 port@0 { 300 port@0 {
301 reg = <0>; 301 reg = <0>;
302 dsi1_in: endpoint { 302 dsi1_in: endpoint {
303 remote-endpoint = <&dp 303 remote-endpoint = <&dpu_intf2_out>;
304 }; 304 };
305 }; 305 };
306 306
307 port@1 { 307 port@1 {
308 reg = <1>; 308 reg = <1>;
309 dsi1_out: endpoint { 309 dsi1_out: endpoint {
310 }; 310 };
311 }; 311 };
312 }; 312 };
313 }; 313 };
314 314
315 dsi1_phy: phy@ae96400 { 315 dsi1_phy: phy@ae96400 {
316 compatible = "qcom,sm8650-dsi-phy- 316 compatible = "qcom,sm8650-dsi-phy-4nm";
317 reg = <0x0ae97000 0x200>, 317 reg = <0x0ae97000 0x200>,
318 <0x0ae97200 0x280>, 318 <0x0ae97200 0x280>,
319 <0x0ae97500 0x400>; 319 <0x0ae97500 0x400>;
320 reg-names = "dsi_phy", 320 reg-names = "dsi_phy",
321 "dsi_phy_lane", 321 "dsi_phy_lane",
322 "dsi_pll"; 322 "dsi_pll";
323 323
324 #clock-cells = <1>; 324 #clock-cells = <1>;
325 #phy-cells = <0>; 325 #phy-cells = <0>;
326 326
327 clocks = <&dispcc_iface_clk>, 327 clocks = <&dispcc_iface_clk>,
328 <&rpmhcc_ref_clk>; 328 <&rpmhcc_ref_clk>;
329 clock-names = "iface", "ref"; 329 clock-names = "iface", "ref";
330 }; 330 };
331 }; 331 };
332 ... 332 ...
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