1 Rockchip RK3399 specific extensions to the cdn
2 ================================
3
4 Required properties:
5 - compatible: must be "rockchip,rk3399-cdn-dp"
6
7 - reg: physical base address of the controller
8
9 - clocks: from common clock binding: handle to
10
11 - clock-names: from common clock binding:
12 Required elements: "core-clk" "
13
14 - resets : a list of phandle + reset specifier
15 - reset-names : string of reset names
16 Required elements: "apb", "cor
17 - power-domains : power-domain property define
18 to respective power domain.
19 - assigned-clocks: main clock, should be <&cru
20 - assigned-clock-rates : the DP core clk frequ
21
22 - rockchip,grf: this soc should set GRF regs,
23
24 - ports: contain a port nodes with endpoint de
25 Documentation/devicetree/bindings/med
26 contained 2 endpoints, connecting to
27
28 - phys: from general PHY binding: the phandle
29
30 - extcon: extcon specifier for the Power Deliv
31
32 - #sound-dai-cells = it must be 1 if your syst
33
34 ----------------------------------------------
35
36 Example:
37 cdn_dp: dp@fec00000 {
38 compatible = "rockchip,rk3399-
39 reg = <0x0 0xfec00000 0x0 0x10
40 interrupts = <GIC_SPI 9 IRQ_TY
41 clocks = <&cru SCLK_DP_CORE>,
42 <&cru SCLK_SPDIF_REC_
43 clock-names = "core-clk", "pcl
44 assigned-clocks = <&cru SCLK_D
45 assigned-clock-rates = <100000
46 power-domains = <&power RK3399
47 phys = <&tcphy0_dp>, <&tcphy1_
48 resets = <&cru SRST_DPTX_SPDIF
49 reset-names = "spdif";
50 extcon = <&fusb0>, <&fusb1>;
51 rockchip,grf = <&grf>;
52 #address-cells = <1>;
53 #size-cells = <0>;
54 #sound-dai-cells = <1>;
55
56 ports {
57 #address-cells = <1>;
58 #size-cells = <0>;
59
60 dp_in: port {
61 #address-cells
62 #size-cells =
63 dp_in_vopb: en
64 reg =
65 remote
66 };
67
68 dp_in_vopl: en
69 reg =
70 remote
71 };
72 };
73 };
74 };
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