1 # SPDX-License-Identifier: GPL-2.0-only 1 # SPDX-License-Identifier: GPL-2.0-only
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/display/sam 4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos5433-mic.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Samsung Exynos5433 SoC Mobile Image Com 7 title: Samsung Exynos5433 SoC Mobile Image Compressor (MIC)
8 8
9 maintainers: 9 maintainers:
10 - Inki Dae <inki.dae@samsung.com> 10 - Inki Dae <inki.dae@samsung.com>
11 - Seung-Woo Kim <sw0312.kim@samsung.com> 11 - Seung-Woo Kim <sw0312.kim@samsung.com>
12 - Kyungmin Park <kyungmin.park@samsung.com> 12 - Kyungmin Park <kyungmin.park@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org> 13 - Krzysztof Kozlowski <krzk@kernel.org>
14 14
15 description: | 15 description: |
16 MIC (Mobile Image Compressor) resides betwee 16 MIC (Mobile Image Compressor) resides between DECON and MIPI DSI. MIPI DSI is
17 not capable of transferring high resoltuion 17 not capable of transferring high resoltuion frame data as DECON can send. MIC
18 solves this problem by compressing the frame 18 solves this problem by compressing the frame data by 1/2 before it is
19 transferred through MIPI DSI. The compressed 19 transferred through MIPI DSI. The compressed frame data must be uncompressed
20 in the panel PCB. 20 in the panel PCB.
21 21
22 properties: 22 properties:
23 compatible: 23 compatible:
24 const: samsung,exynos5433-mic 24 const: samsung,exynos5433-mic
25 25
26 clocks: 26 clocks:
27 maxItems: 2 27 maxItems: 2
28 28
29 clock-names: 29 clock-names:
30 items: 30 items:
31 - const: pclk_mic0 31 - const: pclk_mic0
32 - const: sclk_rgb_vclk_to_mic0 32 - const: sclk_rgb_vclk_to_mic0
33 33
34 ports: 34 ports:
35 $ref: /schemas/graph.yaml#/properties/port 35 $ref: /schemas/graph.yaml#/properties/ports
36 description: 36 description:
37 Contains a port which is connected to mi 37 Contains a port which is connected to mic node.
38 38
39 power-domains: 39 power-domains:
40 maxItems: 1 40 maxItems: 1
41 41
42 reg: 42 reg:
43 maxItems: 1 43 maxItems: 1
44 44
45 samsung,disp-syscon: 45 samsung,disp-syscon:
46 $ref: /schemas/types.yaml#/definitions/pha 46 $ref: /schemas/types.yaml#/definitions/phandle
47 description: 47 description:
48 Phandle to DISP system controller interf 48 Phandle to DISP system controller interface.
49 49
50 required: 50 required:
51 - compatible 51 - compatible
52 - clocks 52 - clocks
53 - clock-names 53 - clock-names
54 - ports 54 - ports
55 - reg 55 - reg
56 - samsung,disp-syscon 56 - samsung,disp-syscon
57 57
58 additionalProperties: false 58 additionalProperties: false
59 59
60 examples: 60 examples:
61 - | 61 - |
62 #include <dt-bindings/clock/exynos5433.h> 62 #include <dt-bindings/clock/exynos5433.h>
63 #include <dt-bindings/interrupt-controller 63 #include <dt-bindings/interrupt-controller/arm-gic.h>
64 64
65 image-processor@13930000 { 65 image-processor@13930000 {
66 compatible = "samsung,exynos5433-mic"; 66 compatible = "samsung,exynos5433-mic";
67 reg = <0x13930000 0x48>; 67 reg = <0x13930000 0x48>;
68 clocks = <&cmu_disp CLK_PCLK_MIC0>, 68 clocks = <&cmu_disp CLK_PCLK_MIC0>,
69 <&cmu_disp CLK_SCLK_RGB_VCLK_ 69 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>;
70 clock-names = "pclk_mic0", 70 clock-names = "pclk_mic0",
71 "sclk_rgb_vclk_to_mic0"; 71 "sclk_rgb_vclk_to_mic0";
72 power-domains = <&pd_disp>; 72 power-domains = <&pd_disp>;
73 samsung,disp-syscon = <&syscon_disp>; 73 samsung,disp-syscon = <&syscon_disp>;
74 74
75 ports { 75 ports {
76 #address-cells = <1>; 76 #address-cells = <1>;
77 #size-cells = <0>; 77 #size-cells = <0>;
78 78
79 port@0 { 79 port@0 {
80 reg = <0>; 80 reg = <0>;
81 mic_to_decon: endpoint { 81 mic_to_decon: endpoint {
82 remote-endpoint = <&decon_ 82 remote-endpoint = <&decon_to_mic>;
83 }; 83 };
84 }; 84 };
85 85
86 port@1 { 86 port@1 {
87 reg = <1>; 87 reg = <1>;
88 mic_to_dsi: endpoint { 88 mic_to_dsi: endpoint {
89 remote-endpoint = <&dsi_to 89 remote-endpoint = <&dsi_to_mic>;
90 }; 90 };
91 }; 91 };
92 }; 92 };
93 }; 93 };
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