1 STMicroelectronics stih4xx platforms
2
3 - sti-vtg: video timing generator
4 Required properties:
5 - compatible: "st,vtg"
6 - reg: Physical base address of the IP regis
7 Optional properties:
8 - interrupts : VTG interrupt number to the C
9 - st,slave: phandle on a slave vtg
10
11 - sti-vtac: video timing advanced inter dye co
12 Required properties:
13 - compatible: "st,vtac-main" or "st,vtac-aux
14 - reg: Physical base address of the IP regis
15 - clocks: from common clock binding: handle
16 number of clocks may depend of the SoC typ
17 See ../clocks/clock-bindings.txt for detai
18 - clock-names: names of the clocks listed in
19 order.
20
21 - sti-display-subsystem: Master device for DRM
22 This device must be the parent of all the su
23 of bind them.
24 Required properties:
25 - compatible: "st,sti-display-subsystem"
26 - ranges: to allow probing of subdevices
27
28 - sti-compositor: frame compositor engine
29 must be a child of sti-display-subsystem
30 Required properties:
31 - compatible: "st,stih<chip>-compositor"
32 - reg: Physical base address of the IP regis
33 - clocks: from common clock binding: handle
34 number of clocks may depend of the SoC typ
35 See ../clocks/clock-bindings.txt for detai
36 - clock-names: names of the clocks listed in
37 order.
38 - resets: resets to be used by the device
39 See ../reset/reset.txt for details.
40 - reset-names: names of the resets listed in
41 order.
42 - st,vtg: phandle(s) on vtg device (main and
43
44 - sti-tvout: video out hardware block
45 must be a child of sti-display-subsystem
46 Required properties:
47 - compatible: "st,stih<chip>-tvout"
48 - reg: Physical base address of the IP regis
49 - reg-names: names of the mapped memory regi
50 the same order.
51 - resets: resets to be used by the device
52 See ../reset/reset.txt for details.
53 - reset-names: names of the resets listed in
54 order.
55
56 - sti-hdmi: hdmi output block
57 must be a child of sti-display-subsystem
58 Required properties:
59 - compatible: "st,stih<chip>-hdmi";
60 - reg: Physical base address of the IP regis
61 - reg-names: names of the mapped memory regi
62 the same order.
63 - interrupts : HDMI interrupt number to the
64 - interrupt-names: names of the interrupts l
65 the same order
66 - clocks: from common clock binding: handle
67 number of clocks may depend of the SoC typ
68 - clock-names: names of the clocks listed in
69 order.
70 - ddc: phandle of an I2C controller used for
71
72 sti-hda:
73 Required properties:
74 must be a child of sti-display-subsystem
75 - compatible: "st,stih<chip>-hda"
76 - reg: Physical base address of the IP regis
77 - reg-names: names of the mapped memory regi
78 the same order.
79 - clocks: from common clock binding: handle
80 number of clocks may depend of the SoC typ
81 See ../clocks/clock-bindings.txt for detai
82 - clock-names: names of the clocks listed in
83 order.
84
85 sti-dvo:
86 Required properties:
87 must be a child of sti-display-subsystem
88 - compatible: "st,stih<chip>-dvo"
89 - reg: Physical base address of the IP regis
90 - reg-names: names of the mapped memory regi
91 the same order.
92 - clocks: from common clock binding: handle
93 number of clocks may depend of the SoC typ
94 See ../clocks/clock-bindings.txt for detai
95 - clock-names: names of the clocks listed in
96 order.
97 - pinctrl-0: pin control handle
98 - pinctrl-names: names of the pin control st
99 - sti,panel: phandle of the panel connected
100
101 sti-hqvdp:
102 must be a child of sti-display-subsystem
103 Required properties:
104 - compatible: "st,stih<chip>-hqvdp"
105 - reg: Physical base address of the IP regis
106 - clocks: from common clock binding: handle
107 number of clocks may depend of the SoC typ
108 See ../clocks/clock-bindings.txt for detai
109 - clock-names: names of the clocks listed in
110 order.
111 - resets: resets to be used by the device
112 See ../reset/reset.txt for details.
113 - reset-names: names of the resets listed in
114 order.
115 - st,vtg: phandle on vtg main device node.
116
117 Example:
118
119 / {
120 ...
121
122 vtg_main_slave: sti-vtg-main-slave@fe8
123 compatible = "st,vtg";
124 reg = <0xfe85A800
125 interrupts = <GIC_SPI 175
126 };
127
128 vtg_main: sti-vtg-main-master@fd348000
129 compatible = "st,vtg";
130 reg = <0xfd348000
131 st,slave = <&vtg_main_s
132 };
133
134 vtg_aux_slave: sti-vtg-aux-slave@fd348
135 compatible = "st,vtg";
136 reg = <0xfe858200
137 interrupts = <GIC_SPI 176
138 };
139
140 vtg_aux: sti-vtg-aux-master@fd348400 {
141 compatible = "st,vtg";
142 reg = <0xfd348400
143 st,slave = <&vtg_aux_sl
144 };
145
146
147 sti-vtac-rx-main@fee82800 {
148 compatible = "st,vtac-mai
149 reg = <0xfee82800
150 clock-names = "vtac";
151 clocks = <&clk_m_a2_d
152 };
153
154 sti-vtac-rx-aux@fee82a00 {
155 compatible = "st,vtac-aux
156 reg = <0xfee82a00
157 clock-names = "vtac";
158 clocks = <&clk_m_a2_d
159 };
160
161 sti-vtac-tx-main@fd349000 {
162 compatible = "st,vtac-mai
163 reg = <0xfd349000
164 clock-names = "vtac";
165 clocks = <&clk_s_a1_
166 };
167
168 sti-vtac-tx-aux@fd349200 {
169 compatible = "st,vtac-aux
170 reg = <0xfd349200
171 clock-names = "vtac";
172 clocks = <&clk_s_a1_h
173 };
174
175 sti-display-subsystem {
176 compatible = "st,sti-display-s
177 ranges;
178
179 sti-compositor@fd340000 {
180 compatible = "st,
181 reg = <0xf
182 clock-names = "com
183 "pix
184 clocks = <&cl
185 <&cl
186 reset-names = "com
187 resets = <&so
188 st,vtg = <&vt
189 };
190
191 sti-tvout@fe000000 {
192 compatible = "st,
193 reg = <0xf
194 reg-names = "tvo
195 reset-names = "tvo
196 resets = <&so
197 };
198
199 sti-hdmi@fe85c000 {
200 compatible = "st,
201 reg = <0xf
202 reg-names = "hdm
203 interrupts = <GIC
204 interrupt-names = "irq
205 clock-names = "pix
206 clocks = <&cl
207 };
208
209 sti-hda@fe85a000 {
210 compatible = "st,
211 reg = <0xf
212 reg-names = "hda
213 clock-names = "pix
214 clocks = <&cl
215 };
216
217 sti-dvo@8d00400 {
218 compatible = "st,
219 reg = <0x8
220 reg-names = "dvo
221 clock-names = "dvo
222 "mai
223 clocks = <&cl
224 <&cl
225 pinctrl-names = "def
226 pinctrl-0 = <&pi
227 sti,panel = <&pa
228 };
229
230 sti-hqvdp@9c000000 {
231 compatible
232 reg
233 clock-names
234 clocks
235 reset-names
236 resets
237 st,vtg
238 };
239 };
240 ...
241 };
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