1 Texas Instruments DRA7x Display Subsystem 1 Texas Instruments DRA7x Display Subsystem
2 ========================================= 2 =========================================
3 3
4 See Documentation/devicetree/bindings/display/ 4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
5 description about OMAP Display Subsystem bindi 5 description about OMAP Display Subsystem bindings.
6 6
7 DSS Core 7 DSS Core
8 -------- 8 --------
9 9
10 Required properties: 10 Required properties:
11 - compatible: "ti,dra7-dss" 11 - compatible: "ti,dra7-dss"
12 - reg: address and length of the register spac 12 - reg: address and length of the register spaces for 'dss'
13 - ti,hwmods: "dss_core" 13 - ti,hwmods: "dss_core"
14 - clocks: handle to fclk 14 - clocks: handle to fclk
15 - clock-names: "fck" 15 - clock-names: "fck"
16 - syscon: phandle to control module core sysco 16 - syscon: phandle to control module core syscon node
17 17
18 Optional properties: 18 Optional properties:
19 19
20 Some DRA7xx SoCs have one dedicated video PLL, 20 Some DRA7xx SoCs have one dedicated video PLL, some have two. These properties
21 can be used to describe the video PLLs: 21 can be used to describe the video PLLs:
22 22
23 - reg: address and length of the register spac 23 - reg: address and length of the register spaces for 'pll1_clkctrl',
24 'pll1', 'pll2_clkctrl', 'pll2' 24 'pll1', 'pll2_clkctrl', 'pll2'
25 - clocks: handle to video1 pll clock and video 25 - clocks: handle to video1 pll clock and video2 pll clock
26 - clock-names: "video1_clk" and "video2_clk" 26 - clock-names: "video1_clk" and "video2_clk"
27 27
28 Required nodes: 28 Required nodes:
29 - DISPC 29 - DISPC
30 30
31 Optional nodes: 31 Optional nodes:
32 - DSS Submodules: HDMI 32 - DSS Submodules: HDMI
33 - Video port for DPI output 33 - Video port for DPI output
34 34
35 DPI Endpoint required properties: 35 DPI Endpoint required properties:
36 - data-lines: number of lines used 36 - data-lines: number of lines used
37 37
38 38
39 DISPC 39 DISPC
40 ----- 40 -----
41 41
42 Required properties: 42 Required properties:
43 - compatible: "ti,dra7-dispc" 43 - compatible: "ti,dra7-dispc"
44 - reg: address and length of the register spac 44 - reg: address and length of the register space
45 - ti,hwmods: "dss_dispc" 45 - ti,hwmods: "dss_dispc"
46 - interrupts: the DISPC interrupt 46 - interrupts: the DISPC interrupt
47 - clocks: handle to fclk 47 - clocks: handle to fclk
48 - clock-names: "fck" 48 - clock-names: "fck"
49 49
50 Optional properties: 50 Optional properties:
51 - max-memory-bandwidth: Input memory (from mai 51 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
52 in bytes per second 52 in bytes per second
53 53
54 54
55 HDMI 55 HDMI
56 ---- 56 ----
57 57
58 Required properties: 58 Required properties:
59 - compatible: "ti,dra7-hdmi" 59 - compatible: "ti,dra7-hdmi"
60 - reg: addresses and lengths of the register s 60 - reg: addresses and lengths of the register spaces for 'wp', 'pll', 'phy',
61 'core' 61 'core'
62 - reg-names: "wp", "pll", "phy", "core" 62 - reg-names: "wp", "pll", "phy", "core"
63 - interrupts: the HDMI interrupt line 63 - interrupts: the HDMI interrupt line
64 - ti,hwmods: "dss_hdmi" 64 - ti,hwmods: "dss_hdmi"
65 - vdda-supply: vdda power supply 65 - vdda-supply: vdda power supply
66 - clocks: handles to fclk and pll clock 66 - clocks: handles to fclk and pll clock
67 - clock-names: "fck", "sys_clk" 67 - clock-names: "fck", "sys_clk"
68 68
69 Optional nodes: 69 Optional nodes:
70 - Video port for HDMI output 70 - Video port for HDMI output
71 71
72 HDMI Endpoint optional properties: 72 HDMI Endpoint optional properties:
73 - lanes: list of 8 pin numbers for the HDMI la 73 - lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-,
74 D1+, D1-, D2+, D2-. (default: 0,1,2,3,4,5,6, 74 D1+, D1-, D2+, D2-. (default: 0,1,2,3,4,5,6,7)
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