1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/display/xln 4 $id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Xilinx ZynqMP DisplayPort Subsystem 7 title: Xilinx ZynqMP DisplayPort Subsystem
8 8
9 description: | 9 description: |
10 The DisplayPort subsystem of Xilinx ZynqMP ( 10 The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)
11 implements the display and audio pipelines b 11 implements the display and audio pipelines based on the DisplayPort v1.2
12 standard. The subsystem includes multiple fu 12 standard. The subsystem includes multiple functional blocks as below:
13 13
14 +------------------------------ 14 +------------------------------------------------------------+
15 +--------+ | +----------------+ +----- 15 +--------+ | +----------------+ +-----------+ |
16 | DPDMA | --->| | --> | Vi 16 | DPDMA | --->| | --> | Video | Video +-------------+ |
17 | 4x vid | | | | | Rend 17 | 4x vid | | | | | Rendering | -+--> | | | +------+
18 | 2x aud | | | Audio/Video | --> | Pipe 18 | 2x aud | | | Audio/Video | --> | Pipeline | | | DisplayPort |---> | PHY0 |
19 +--------+ | | Buffer Manager | +----- 19 +--------+ | | Buffer Manager | +-----------+ | | Source | | +------+
20 | | and STC | +----- 20 | | and STC | +-----------+ | | Controller | | +------+
21 Live Video --->| | --> | Au 21 Live Video --->| | --> | Audio | Audio | |---> | PHY1 |
22 | | | | Mi 22 | | | | Mixer | --+-> | | | +------+
23 Live Audio --->| | --> | 23 Live Audio --->| | --> | | || +-------------+ |
24 | +----------------+ +----- 24 | +----------------+ +-----------+ || |
25 +------------------------------ 25 +---------------------------------------||-------------------+
26 26 vv
27 27 Blended Video and
28 28 Mixed Audio to PL
29 29
30 The Buffer Manager interacts with external i 30 The Buffer Manager interacts with external interface such as DMA engines or
31 live audio/video streams from the programmab 31 live audio/video streams from the programmable logic. The Video Rendering
32 Pipeline blends the video and graphics layer 32 Pipeline blends the video and graphics layers and performs colorspace
33 conversion. The Audio Mixer mixes the incomi 33 conversion. The Audio Mixer mixes the incoming audio streams. The DisplayPort
34 Source Controller handles the DisplayPort pr 34 Source Controller handles the DisplayPort protocol and connects to external
35 PHYs. 35 PHYs.
36 36
37 The subsystem supports 2 video and 2 audio s 37 The subsystem supports 2 video and 2 audio streams, and various pixel formats
38 and depths up to 4K@30 resolution. 38 and depths up to 4K@30 resolution.
39 39
40 Please refer to "Zynq UltraScale+ Device Tec 40 Please refer to "Zynq UltraScale+ Device Technical Reference Manual"
41 (https://www.xilinx.com/support/documentatio 41 (https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf)
42 for more details. 42 for more details.
43 43
44 maintainers: 44 maintainers:
45 - Laurent Pinchart <laurent.pinchart@ideasonb 45 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
46 46
47 properties: 47 properties:
48 compatible: 48 compatible:
49 const: xlnx,zynqmp-dpsub-1.7 49 const: xlnx,zynqmp-dpsub-1.7
50 50
51 reg: 51 reg:
52 maxItems: 4 52 maxItems: 4
53 reg-names: 53 reg-names:
54 items: 54 items:
55 - const: dp 55 - const: dp
56 - const: blend 56 - const: blend
57 - const: av_buf 57 - const: av_buf
58 - const: aud 58 - const: aud
59 59
60 interrupts: 60 interrupts:
61 maxItems: 1 61 maxItems: 1
62 62
63 clocks: 63 clocks:
64 description: 64 description:
65 The APB clock and at least one video clo 65 The APB clock and at least one video clock are mandatory, the audio clock
66 is optional. 66 is optional.
67 minItems: 2 67 minItems: 2
68 items: 68 items:
69 - description: dp_apb_clk is the APB clo 69 - description: dp_apb_clk is the APB clock
70 - description: dp_aud_clk is the Audio c 70 - description: dp_aud_clk is the Audio clock
71 - description: 71 - description:
72 dp_vtc_pixel_clk_in is the non-live 72 dp_vtc_pixel_clk_in is the non-live video clock (from Processing
73 System) 73 System)
74 - description: 74 - description:
75 dp_live_video_in_clk is the live vid 75 dp_live_video_in_clk is the live video clock (from Programmable
76 Logic) 76 Logic)
77 clock-names: 77 clock-names:
78 oneOf: 78 oneOf:
79 - minItems: 2 79 - minItems: 2
80 items: 80 items:
81 - const: dp_apb_clk 81 - const: dp_apb_clk
82 - enum: [ dp_vtc_pixel_clk_in, dp_li 82 - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
83 - enum: [ dp_vtc_pixel_clk_in, dp_li 83 - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
84 - minItems: 3 84 - minItems: 3
85 items: 85 items:
86 - const: dp_apb_clk 86 - const: dp_apb_clk
87 - const: dp_aud_clk 87 - const: dp_aud_clk
88 - enum: [ dp_vtc_pixel_clk_in, dp_li 88 - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
89 - enum: [ dp_vtc_pixel_clk_in, dp_li 89 - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
90 90
91 power-domains: 91 power-domains:
92 maxItems: 1 92 maxItems: 1
93 93
94 resets: 94 resets:
95 maxItems: 1 95 maxItems: 1
96 96
97 dmas: 97 dmas:
98 items: 98 items:
99 - description: Video layer, plane 0 (RGB 99 - description: Video layer, plane 0 (RGB or luma)
100 - description: Video layer, plane 1 (U/V 100 - description: Video layer, plane 1 (U/V or U)
101 - description: Video layer, plane 2 (V) 101 - description: Video layer, plane 2 (V)
102 - description: Graphics layer 102 - description: Graphics layer
103 dma-names: 103 dma-names:
104 items: 104 items:
105 - const: vid0 105 - const: vid0
106 - const: vid1 106 - const: vid1
107 - const: vid2 107 - const: vid2
108 - const: gfx0 108 - const: gfx0
109 109
110 phys: 110 phys:
111 description: PHYs for the DP data lanes 111 description: PHYs for the DP data lanes
112 minItems: 1 112 minItems: 1
113 maxItems: 2 113 maxItems: 2
114 phy-names: 114 phy-names:
115 minItems: 1 115 minItems: 1
116 items: 116 items:
117 - const: dp-phy0 117 - const: dp-phy0
118 - const: dp-phy1 118 - const: dp-phy1
119 119
120 ports: 120 ports:
121 $ref: /schemas/graph.yaml#/properties/port 121 $ref: /schemas/graph.yaml#/properties/ports
122 description: | 122 description: |
123 Connections to the programmable logic an 123 Connections to the programmable logic and the DisplayPort PHYs. Each port
124 shall have a single endpoint. 124 shall have a single endpoint.
125 125
126 properties: 126 properties:
127 port@0: 127 port@0:
128 $ref: /schemas/graph.yaml#/properties/ 128 $ref: /schemas/graph.yaml#/properties/port
129 description: The live video input from 129 description: The live video input from the programmable logic
130 130
131 port@1: 131 port@1:
132 $ref: /schemas/graph.yaml#/properties/ 132 $ref: /schemas/graph.yaml#/properties/port
133 description: The live graphics input f 133 description: The live graphics input from the programmable logic
134 134
135 port@2: 135 port@2:
136 $ref: /schemas/graph.yaml#/properties/ 136 $ref: /schemas/graph.yaml#/properties/port
137 description: The live audio input from 137 description: The live audio input from the programmable logic
138 138
139 port@3: 139 port@3:
140 $ref: /schemas/graph.yaml#/properties/ 140 $ref: /schemas/graph.yaml#/properties/port
141 description: The blended video output 141 description: The blended video output to the programmable logic
142 142
143 port@4: 143 port@4:
144 $ref: /schemas/graph.yaml#/properties/ 144 $ref: /schemas/graph.yaml#/properties/port
145 description: The mixed audio output to 145 description: The mixed audio output to the programmable logic
146 146
147 port@5: 147 port@5:
148 $ref: /schemas/graph.yaml#/properties/ 148 $ref: /schemas/graph.yaml#/properties/port
149 description: The DisplayPort output 149 description: The DisplayPort output
150 150
151 required: 151 required:
152 - port@0 152 - port@0
153 - port@1 153 - port@1
154 - port@2 154 - port@2
155 - port@3 155 - port@3
156 - port@4 156 - port@4
157 - port@5 157 - port@5
158 158
159 required: 159 required:
160 - compatible 160 - compatible
161 - reg 161 - reg
162 - reg-names 162 - reg-names
163 - interrupts 163 - interrupts
164 - clocks 164 - clocks
165 - clock-names 165 - clock-names
166 - power-domains 166 - power-domains
167 - resets 167 - resets
168 - dmas 168 - dmas
169 - dma-names 169 - dma-names
170 - phys 170 - phys
171 - phy-names 171 - phy-names
172 - ports 172 - ports
173 173
174 additionalProperties: false 174 additionalProperties: false
175 175
176 examples: 176 examples:
177 - | 177 - |
178 #include <dt-bindings/phy/phy.h> 178 #include <dt-bindings/phy/phy.h>
179 #include <dt-bindings/reset/xlnx-zynqmp-re 179 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
180 180
181 display@fd4a0000 { 181 display@fd4a0000 {
182 compatible = "xlnx,zynqmp-dpsub-1.7"; 182 compatible = "xlnx,zynqmp-dpsub-1.7";
183 reg = <0xfd4a0000 0x1000>, 183 reg = <0xfd4a0000 0x1000>,
184 <0xfd4aa000 0x1000>, 184 <0xfd4aa000 0x1000>,
185 <0xfd4ab000 0x1000>, 185 <0xfd4ab000 0x1000>,
186 <0xfd4ac000 0x1000>; 186 <0xfd4ac000 0x1000>;
187 reg-names = "dp", "blend", "av_buf", " 187 reg-names = "dp", "blend", "av_buf", "aud";
188 interrupts = <0 119 4>; 188 interrupts = <0 119 4>;
189 interrupt-parent = <&gic>; 189 interrupt-parent = <&gic>;
190 190
191 clock-names = "dp_apb_clk", "dp_aud_cl 191 clock-names = "dp_apb_clk", "dp_aud_clk", "dp_live_video_in_clk";
192 clocks = <&dp_aclk>, <&clkc 17>, <&si5 192 clocks = <&dp_aclk>, <&clkc 17>, <&si570_1>;
193 193
194 power-domains = <&pd_dp>; 194 power-domains = <&pd_dp>;
195 resets = <&reset ZYNQMP_RESET_DP>; 195 resets = <&reset ZYNQMP_RESET_DP>;
196 196
197 dma-names = "vid0", "vid1", "vid2", "g 197 dma-names = "vid0", "vid1", "vid2", "gfx0";
198 dmas = <&xlnx_dpdma 0>, 198 dmas = <&xlnx_dpdma 0>,
199 <&xlnx_dpdma 1>, 199 <&xlnx_dpdma 1>,
200 <&xlnx_dpdma 2>, 200 <&xlnx_dpdma 2>,
201 <&xlnx_dpdma 3>; 201 <&xlnx_dpdma 3>;
202 202
203 phys = <&psgtr 1 PHY_TYPE_DP 0 3>, 203 phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
204 <&psgtr 0 PHY_TYPE_DP 1 3>; 204 <&psgtr 0 PHY_TYPE_DP 1 3>;
205 205
206 phy-names = "dp-phy0", "dp-phy1"; 206 phy-names = "dp-phy0", "dp-phy1";
207 207
208 ports { 208 ports {
209 #address-cells = <1>; 209 #address-cells = <1>;
210 #size-cells = <0>; 210 #size-cells = <0>;
211 211
212 port@0 { 212 port@0 {
213 reg = <0>; 213 reg = <0>;
214 }; 214 };
215 port@1 { 215 port@1 {
216 reg = <1>; 216 reg = <1>;
217 }; 217 };
218 port@2 { 218 port@2 {
219 reg = <2>; 219 reg = <2>;
220 }; 220 };
221 port@3 { 221 port@3 {
222 reg = <3>; 222 reg = <3>;
223 }; 223 };
224 port@4 { 224 port@4 {
225 reg = <4>; 225 reg = <4>;
226 }; 226 };
227 port@5 { 227 port@5 {
228 reg = <5>; 228 reg = <5>;
229 dpsub_dp_out: endpoint { 229 dpsub_dp_out: endpoint {
230 remote-endpoint = <&dp_con 230 remote-endpoint = <&dp_connector>;
231 }; 231 };
232 }; 232 };
233 }; 233 };
234 }; 234 };
235 235
236 ... 236 ...
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