1 Analog Devices AXI-DMAC DMA controller !! 1 Analog Device AXI-DMAC DMA controller
2 2
3 Required properties: 3 Required properties:
4 - compatible: Must be "adi,axi-dmac-1.00.a". 4 - compatible: Must be "adi,axi-dmac-1.00.a".
5 - reg: Specification for the controllers memo 5 - reg: Specification for the controllers memory mapped register map.
6 - interrupts: Specification for the controlle 6 - interrupts: Specification for the controllers interrupt.
7 - clocks: Phandle and specifier to the contro 7 - clocks: Phandle and specifier to the controllers AXI interface clock
8 - #dma-cells: Must be 1. 8 - #dma-cells: Must be 1.
9 9
10 Required sub-nodes: 10 Required sub-nodes:
11 - adi,channels: This sub-node must contain a 11 - adi,channels: This sub-node must contain a sub-node for each DMA channel. For
12 the channel sub-nodes the following binding 12 the channel sub-nodes the following bindings apply. They must match the
13 configuration options of the peripheral as 13 configuration options of the peripheral as it was instantiated.
14 14
15 Required properties for adi,channels sub-node: 15 Required properties for adi,channels sub-node:
16 - #size-cells: Must be 0 16 - #size-cells: Must be 0
17 - #address-cells: Must be 1 17 - #address-cells: Must be 1
18 18
19 Required channel sub-node properties: 19 Required channel sub-node properties:
20 - reg: Which channel this node refers to. 20 - reg: Which channel this node refers to.
>> 21 - adi,length-width: Width of the DMA transfer length register.
21 - adi,source-bus-width, 22 - adi,source-bus-width,
22 adi,destination-bus-width: Width of the sou 23 adi,destination-bus-width: Width of the source or destination bus in bits.
23 - adi,source-bus-type, 24 - adi,source-bus-type,
24 adi,destination-bus-type: Type of the sourc 25 adi,destination-bus-type: Type of the source or destination bus. Must be one
25 of the following: 26 of the following:
26 0 (AXI_DMAC_TYPE_AXI_MM): Memory mappe 27 0 (AXI_DMAC_TYPE_AXI_MM): Memory mapped AXI interface
27 1 (AXI_DMAC_TYPE_AXI_STREAM): Streamin 28 1 (AXI_DMAC_TYPE_AXI_STREAM): Streaming AXI interface
28 2 (AXI_DMAC_TYPE_AXI_FIFO): FIFO inter 29 2 (AXI_DMAC_TYPE_AXI_FIFO): FIFO interface
29 30
30 Deprecated optional channel properties: !! 31 Optional channel properties:
31 - adi,length-width: Width of the DMA transfer <<
32 - adi,cyclic: Must be set if the channel supp 32 - adi,cyclic: Must be set if the channel supports hardware cyclic DMA
33 transfers. 33 transfers.
34 - adi,2d: Must be set if the channel supports 34 - adi,2d: Must be set if the channel supports hardware 2D DMA transfers.
35 35
36 DMA clients connected to the AXI-DMAC DMA cont 36 DMA clients connected to the AXI-DMAC DMA controller must use the format
37 described in the dma.txt file using a one-cell 37 described in the dma.txt file using a one-cell specifier. The value of the
38 specifier refers to the DMA channel index. 38 specifier refers to the DMA channel index.
39 39
40 Example: 40 Example:
41 41
42 dma: dma@7c420000 { 42 dma: dma@7c420000 {
43 compatible = "adi,axi-dmac-1.00.a"; 43 compatible = "adi,axi-dmac-1.00.a";
44 reg = <0x7c420000 0x10000>; 44 reg = <0x7c420000 0x10000>;
45 interrupts = <0 57 0>; 45 interrupts = <0 57 0>;
46 clocks = <&clkc 16>; 46 clocks = <&clkc 16>;
47 #dma-cells = <1>; 47 #dma-cells = <1>;
48 48
49 adi,channels { 49 adi,channels {
50 #size-cells = <0>; 50 #size-cells = <0>;
51 #address-cells = <1>; 51 #address-cells = <1>;
52 52
53 dma-channel@0 { 53 dma-channel@0 {
54 reg = <0>; 54 reg = <0>;
55 adi,source-bus-width = 55 adi,source-bus-width = <32>;
56 adi,source-bus-type = 56 adi,source-bus-type = <ADI_AXI_DMAC_TYPE_MM_AXI>;
57 adi,destination-bus-wi 57 adi,destination-bus-width = <64>;
58 adi,destination-bus-ty 58 adi,destination-bus-type = <ADI_AXI_DMAC_TYPE_FIFO>;
59 }; 59 };
60 }; 60 };
61 }; 61 };
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