1 * Atmel Direct Memory Access Controller (DMA) 1 * Atmel Direct Memory Access Controller (DMA)
2 2
3 Required properties: 3 Required properties:
4 - compatible: Should be "atmel,<chip>-dma". 4 - compatible: Should be "atmel,<chip>-dma".
5 - reg: Should contain DMA registers location a 5 - reg: Should contain DMA registers location and length.
6 - interrupts: Should contain DMA interrupt. 6 - interrupts: Should contain DMA interrupt.
7 - #dma-cells: Must be <2>, used to represent t 7 - #dma-cells: Must be <2>, used to represent the number of integer cells in
8 the dmas property of client devices. 8 the dmas property of client devices.
9 9
10 Example: 10 Example:
11 11
12 dma0: dma@ffffec00 { 12 dma0: dma@ffffec00 {
13 compatible = "atmel,at91sam9g45-dma"; 13 compatible = "atmel,at91sam9g45-dma";
14 reg = <0xffffec00 0x200>; 14 reg = <0xffffec00 0x200>;
15 interrupts = <21>; 15 interrupts = <21>;
16 #dma-cells = <2>; 16 #dma-cells = <2>;
17 }; 17 };
18 18
19 DMA clients connected to the Atmel DMA control 19 DMA clients connected to the Atmel DMA controller must use the format
20 described in the dma.txt file, using a three-c 20 described in the dma.txt file, using a three-cell specifier for each channel:
21 a phandle plus two integer cells. 21 a phandle plus two integer cells.
22 The three cells in order are: 22 The three cells in order are:
23 23
24 1. A phandle pointing to the DMA controller. 24 1. A phandle pointing to the DMA controller.
25 2. The memory interface (16 most significant b 25 2. The memory interface (16 most significant bits), the peripheral interface
26 (16 less significant bits). 26 (16 less significant bits).
27 3. Parameters for the at91 DMA configuration r 27 3. Parameters for the at91 DMA configuration register which are device
28 dependent: 28 dependent:
29 - bit 7-0: peripheral identifier for the har 29 - bit 7-0: peripheral identifier for the hardware handshaking interface. The
30 identifier can be different for tx and rx. 30 identifier can be different for tx and rx.
31 - bit 11-8: FIFO configuration. 0 for half F 31 - bit 11-8: FIFO configuration. 0 for half FIFO, 1 for ALAP, 2 for ASAP.
32 32
33 Example: 33 Example:
34 34
35 i2c0@i2c@f8010000 { 35 i2c0@i2c@f8010000 {
36 compatible = "atmel,at91sam9x5-i2c"; 36 compatible = "atmel,at91sam9x5-i2c";
37 reg = <0xf8010000 0x100>; 37 reg = <0xf8010000 0x100>;
38 interrupts = <9 4 6>; 38 interrupts = <9 4 6>;
39 dmas = <&dma0 1 7>, 39 dmas = <&dma0 1 7>,
40 <&dma0 1 8>; 40 <&dma0 1 8>;
41 dma-names = "tx", "rx"; 41 dma-names = "tx", "rx";
42 }; 42 };
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