1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/dma/brcm,bc 4 $id: http://devicetree.org/schemas/dma/brcm,bcm2835-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: BCM2835 DMA controller 7 title: BCM2835 DMA controller
8 8
9 maintainers: 9 maintainers:
10 - Nicolas Saenz Julienne <nsaenz@kernel.org> 10 - Nicolas Saenz Julienne <nsaenz@kernel.org>
11 11
12 description: 12 description:
13 The BCM2835 DMA controller has 16 channels i 13 The BCM2835 DMA controller has 16 channels in total. Only the lower
14 13 channels have an associated IRQ. Some arb 14 13 channels have an associated IRQ. Some arbitrary channels are used by the
15 VideoCore firmware (1,3,6,7 in the current f 15 VideoCore firmware (1,3,6,7 in the current firmware version). The channels
16 0, 2 and 3 have special functionality and sh 16 0, 2 and 3 have special functionality and should not be used by the driver.
17 17
18 allOf: 18 allOf:
19 - $ref: dma-controller.yaml# 19 - $ref: dma-controller.yaml#
20 20
21 properties: 21 properties:
22 compatible: 22 compatible:
23 const: brcm,bcm2835-dma 23 const: brcm,bcm2835-dma
24 24
25 reg: 25 reg:
26 maxItems: 1 26 maxItems: 1
27 27
28 interrupts: 28 interrupts:
29 description: 29 description:
30 Should contain the DMA interrupts associ 30 Should contain the DMA interrupts associated to the DMA channels in
31 ascending order. 31 ascending order.
32 minItems: 1 32 minItems: 1
33 maxItems: 16 33 maxItems: 16
34 34
35 interrupt-names: 35 interrupt-names:
36 minItems: 1 36 minItems: 1
37 maxItems: 16 37 maxItems: 16
38 38
39 '#dma-cells': 39 '#dma-cells':
40 description: The single cell represents th 40 description: The single cell represents the DREQ number.
41 const: 1 41 const: 1
42 42
43 brcm,dma-channel-mask: 43 brcm,dma-channel-mask:
44 $ref: /schemas/types.yaml#/definitions/uin 44 $ref: /schemas/types.yaml#/definitions/uint32
45 description: 45 description:
46 Bitmask of available DMA channels in asc 46 Bitmask of available DMA channels in ascending order that are
47 not reserved by firmware and are availab 47 not reserved by firmware and are available to the
48 kernel. i.e. first channel corresponds t 48 kernel. i.e. first channel corresponds to LSB.
49 49
50 unevaluatedProperties: false 50 unevaluatedProperties: false
51 51
52 required: 52 required:
53 - compatible 53 - compatible
54 - reg 54 - reg
55 - interrupts 55 - interrupts
56 - "#dma-cells" 56 - "#dma-cells"
57 - brcm,dma-channel-mask 57 - brcm,dma-channel-mask
58 58
59 examples: 59 examples:
60 - | 60 - |
61 dma-controller@7e007000 { 61 dma-controller@7e007000 {
62 compatible = "brcm,bcm2835-dma"; 62 compatible = "brcm,bcm2835-dma";
63 reg = <0x7e007000 0xf00>; 63 reg = <0x7e007000 0xf00>;
64 interrupts = <1 16>, 64 interrupts = <1 16>,
65 <1 17>, 65 <1 17>,
66 <1 18>, 66 <1 18>,
67 <1 19>, 67 <1 19>,
68 <1 20>, 68 <1 20>,
69 <1 21>, 69 <1 21>,
70 <1 22>, 70 <1 22>,
71 <1 23>, 71 <1 23>,
72 <1 24>, 72 <1 24>,
73 <1 25>, 73 <1 25>,
74 <1 26>, 74 <1 26>,
75 /* dma channel 11-14 share 75 /* dma channel 11-14 share one irq */
76 <1 27>, 76 <1 27>,
77 <1 27>, 77 <1 27>,
78 <1 27>, 78 <1 27>,
79 <1 27>, 79 <1 27>,
80 /* unused shared irq for al 80 /* unused shared irq for all channels */
81 <1 28>; 81 <1 28>;
82 interrupt-names = "dma0", 82 interrupt-names = "dma0",
83 "dma1", 83 "dma1",
84 "dma2", 84 "dma2",
85 "dma3", 85 "dma3",
86 "dma4", 86 "dma4",
87 "dma5", 87 "dma5",
88 "dma6", 88 "dma6",
89 "dma7", 89 "dma7",
90 "dma8", 90 "dma8",
91 "dma9", 91 "dma9",
92 "dma10", 92 "dma10",
93 "dma11", 93 "dma11",
94 "dma12", 94 "dma12",
95 "dma13", 95 "dma13",
96 "dma14", 96 "dma14",
97 "dma-shared-all"; 97 "dma-shared-all";
98 #dma-cells = <1>; 98 #dma-cells = <1>;
99 brcm,dma-channel-mask = <0x7f35>; 99 brcm,dma-channel-mask = <0x7f35>;
100 }; 100 };
101 101
102 ... 102 ...
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