1 * IMG Multi-threaded DMA Controller (MDC) 1 * IMG Multi-threaded DMA Controller (MDC)
2 2
3 Required properties: 3 Required properties:
4 - compatible: Must be "img,pistachio-mdc-dma". 4 - compatible: Must be "img,pistachio-mdc-dma".
5 - reg: Must contain the base address and lengt 5 - reg: Must contain the base address and length of the MDC registers.
6 - interrupts: Must contain all the per-channel 6 - interrupts: Must contain all the per-channel DMA interrupts.
7 - clocks: Must contain an entry for each entry 7 - clocks: Must contain an entry for each entry in clock-names.
8 See ../clock/clock-bindings.txt for details. 8 See ../clock/clock-bindings.txt for details.
9 - clock-names: Must include the following entr 9 - clock-names: Must include the following entries:
10 - sys: MDC system interface clock. 10 - sys: MDC system interface clock.
11 - img,cr-periph: Must contain a phandle to the 11 - img,cr-periph: Must contain a phandle to the peripheral control syscon
12 node which contains the DMA request to chann 12 node which contains the DMA request to channel mapping registers.
13 - img,max-burst-multiplier: Must be the maximu 13 - img,max-burst-multiplier: Must be the maximum supported burst size multiplier.
14 The maximum burst size is this value multipl 14 The maximum burst size is this value multiplied by the hardware-reported bus
15 width. 15 width.
16 - #dma-cells: Must be 3: 16 - #dma-cells: Must be 3:
17 - The first cell is the peripheral's DMA req 17 - The first cell is the peripheral's DMA request line.
18 - The second cell is a bitmap specifying to 18 - The second cell is a bitmap specifying to which channels the DMA request
19 line may be mapped (i.e. bit N set indicat 19 line may be mapped (i.e. bit N set indicates channel N is usable).
20 - The third cell is the thread ID to be used 20 - The third cell is the thread ID to be used by the channel.
21 21
22 Optional properties: 22 Optional properties:
23 - dma-channels: Number of supported DMA channe 23 - dma-channels: Number of supported DMA channels, up to 32. If not specified
24 the number reported by the hardware is used. 24 the number reported by the hardware is used.
25 25
26 Example: 26 Example:
27 27
28 mdc: dma-controller@18143000 { 28 mdc: dma-controller@18143000 {
29 compatible = "img,pistachio-mdc-dma"; 29 compatible = "img,pistachio-mdc-dma";
30 reg = <0x18143000 0x1000>; 30 reg = <0x18143000 0x1000>;
31 interrupts = <GIC_SHARED 27 IRQ_TYPE_L 31 interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>,
32 <GIC_SHARED 28 IRQ_TYPE_L 32 <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>,
33 <GIC_SHARED 29 IRQ_TYPE_L 33 <GIC_SHARED 29 IRQ_TYPE_LEVEL_HIGH>,
34 <GIC_SHARED 30 IRQ_TYPE_L 34 <GIC_SHARED 30 IRQ_TYPE_LEVEL_HIGH>,
35 <GIC_SHARED 31 IRQ_TYPE_L 35 <GIC_SHARED 31 IRQ_TYPE_LEVEL_HIGH>,
36 <GIC_SHARED 32 IRQ_TYPE_L 36 <GIC_SHARED 32 IRQ_TYPE_LEVEL_HIGH>,
37 <GIC_SHARED 33 IRQ_TYPE_L 37 <GIC_SHARED 33 IRQ_TYPE_LEVEL_HIGH>,
38 <GIC_SHARED 34 IRQ_TYPE_L 38 <GIC_SHARED 34 IRQ_TYPE_LEVEL_HIGH>,
39 <GIC_SHARED 35 IRQ_TYPE_L 39 <GIC_SHARED 35 IRQ_TYPE_LEVEL_HIGH>,
40 <GIC_SHARED 36 IRQ_TYPE_L 40 <GIC_SHARED 36 IRQ_TYPE_LEVEL_HIGH>,
41 <GIC_SHARED 37 IRQ_TYPE_L 41 <GIC_SHARED 37 IRQ_TYPE_LEVEL_HIGH>,
42 <GIC_SHARED 38 IRQ_TYPE_L 42 <GIC_SHARED 38 IRQ_TYPE_LEVEL_HIGH>;
43 clocks = <&system_clk>; 43 clocks = <&system_clk>;
44 clock-names = "sys"; 44 clock-names = "sys";
45 45
46 img,max-burst-multiplier = <16>; 46 img,max-burst-multiplier = <16>;
47 img,cr-periph = <&cr_periph>; 47 img,cr-periph = <&cr_periph>;
48 48
49 #dma-cells = <3>; 49 #dma-cells = <3>;
50 }; 50 };
51 51
52 spi@18100f00 { 52 spi@18100f00 {
53 ... 53 ...
54 dmas = <&mdc 9 0xffffffff 0>, <&mdc 10 54 dmas = <&mdc 9 0xffffffff 0>, <&mdc 10 0xffffffff 0>;
55 dma-names = "tx", "rx"; 55 dma-names = "tx", "rx";
56 ... 56 ...
57 }; 57 };
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