1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/dma/intel,l 4 $id: http://devicetree.org/schemas/dma/intel,ldma.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Lightning Mountain centralized DMA cont 7 title: Lightning Mountain centralized DMA controllers.
8 8
9 maintainers: 9 maintainers:
10 - chuanhua.lei@intel.com 10 - chuanhua.lei@intel.com
11 - mallikarjunax.reddy@intel.com 11 - mallikarjunax.reddy@intel.com
12 12
13 allOf: 13 allOf:
14 - $ref: dma-controller.yaml# 14 - $ref: dma-controller.yaml#
15 15
16 properties: 16 properties:
17 compatible: 17 compatible:
18 enum: 18 enum:
19 - intel,lgm-cdma 19 - intel,lgm-cdma
20 - intel,lgm-dma2tx 20 - intel,lgm-dma2tx
21 - intel,lgm-dma1rx 21 - intel,lgm-dma1rx
22 - intel,lgm-dma1tx 22 - intel,lgm-dma1tx
23 - intel,lgm-dma0tx 23 - intel,lgm-dma0tx
24 - intel,lgm-dma3 24 - intel,lgm-dma3
25 - intel,lgm-toe-dma30 25 - intel,lgm-toe-dma30
26 - intel,lgm-toe-dma31 26 - intel,lgm-toe-dma31
27 27
28 reg: 28 reg:
29 maxItems: 1 29 maxItems: 1
30 30
31 "#dma-cells": 31 "#dma-cells":
32 const: 3 32 const: 3
33 description: 33 description:
34 The first cell is the peripheral's DMA r 34 The first cell is the peripheral's DMA request line.
35 The second cell is the peripheral's (por 35 The second cell is the peripheral's (port) number corresponding to the channel.
36 The third cell is the burst length of th 36 The third cell is the burst length of the channel.
37 37
38 dma-channels: 38 dma-channels:
39 minimum: 1 39 minimum: 1
40 maximum: 16 40 maximum: 16
41 41
42 dma-channel-mask: 42 dma-channel-mask:
43 maxItems: 1 43 maxItems: 1
44 44
45 clocks: 45 clocks:
46 maxItems: 1 46 maxItems: 1
47 47
48 resets: 48 resets:
49 maxItems: 1 49 maxItems: 1
50 50
51 reset-names: 51 reset-names:
52 items: 52 items:
53 - const: ctrl 53 - const: ctrl
54 54
55 interrupts: 55 interrupts:
56 maxItems: 1 56 maxItems: 1
57 57
58 intel,dma-poll-cnt: 58 intel,dma-poll-cnt:
59 $ref: /schemas/types.yaml#/definitions/uin 59 $ref: /schemas/types.yaml#/definitions/uint32
60 description: 60 description:
61 DMA descriptor polling counter is used t 61 DMA descriptor polling counter is used to control the poling mechanism
62 for the descriptor fetching for all chan 62 for the descriptor fetching for all channels.
63 63
64 intel,dma-byte-en: 64 intel,dma-byte-en:
65 type: boolean 65 type: boolean
66 description: 66 description:
67 DMA byte enable is only valid for DMA wr 67 DMA byte enable is only valid for DMA write(RX).
68 Byte enable(1) means DMA write will be b 68 Byte enable(1) means DMA write will be based on the number of dwords
69 instead of the whole burst. 69 instead of the whole burst.
70 70
71 intel,dma-drb: 71 intel,dma-drb:
72 type: boolean 72 type: boolean
73 description: 73 description:
74 DMA descriptor read back to make sure da 74 DMA descriptor read back to make sure data and desc synchronization.
75 75
76 intel,dma-dburst-wr: 76 intel,dma-dburst-wr:
77 type: boolean 77 type: boolean
78 description: 78 description:
79 Enable RX dynamic burst write. When it i 79 Enable RX dynamic burst write. When it is enabled, the DMA does RX dynamic burst;
80 if it is disabled, the DMA RX will still 80 if it is disabled, the DMA RX will still support programmable fixed burst size of 2,4,8,16.
81 It only applies to RX DMA and memcopy DM 81 It only applies to RX DMA and memcopy DMA.
82 82
83 required: 83 required:
84 - compatible 84 - compatible
85 - reg 85 - reg
86 86
87 additionalProperties: false 87 additionalProperties: false
88 88
89 examples: 89 examples:
90 - | 90 - |
91 dma0: dma-controller@e0e00000 { 91 dma0: dma-controller@e0e00000 {
92 compatible = "intel,lgm-cdma"; 92 compatible = "intel,lgm-cdma";
93 reg = <0xe0e00000 0x1000>; 93 reg = <0xe0e00000 0x1000>;
94 #dma-cells = <3>; 94 #dma-cells = <3>;
95 dma-channels = <16>; 95 dma-channels = <16>;
96 dma-channel-mask = <0xFFFF>; 96 dma-channel-mask = <0xFFFF>;
97 interrupt-parent = <&ioapic1>; 97 interrupt-parent = <&ioapic1>;
98 interrupts = <82 1>; 98 interrupts = <82 1>;
99 resets = <&rcu0 0x30 0>; 99 resets = <&rcu0 0x30 0>;
100 reset-names = "ctrl"; 100 reset-names = "ctrl";
101 clocks = <&cgu0 80>; 101 clocks = <&cgu0 80>;
102 intel,dma-poll-cnt = <4>; 102 intel,dma-poll-cnt = <4>;
103 intel,dma-byte-en; 103 intel,dma-byte-en;
104 intel,dma-drb; 104 intel,dma-drb;
105 }; 105 };
106 - | 106 - |
107 dma3: dma-controller@ec800000 { 107 dma3: dma-controller@ec800000 {
108 compatible = "intel,lgm-dma3"; 108 compatible = "intel,lgm-dma3";
109 reg = <0xec800000 0x1000>; 109 reg = <0xec800000 0x1000>;
110 clocks = <&cgu0 71>; 110 clocks = <&cgu0 71>;
111 resets = <&rcu0 0x10 9>; 111 resets = <&rcu0 0x10 9>;
112 #dma-cells = <3>; 112 #dma-cells = <3>;
113 intel,dma-poll-cnt = <16>; 113 intel,dma-poll-cnt = <16>;
114 intel,dma-byte-en; 114 intel,dma-byte-en;
115 intel,dma-dburst-wr; 115 intel,dma-dburst-wr;
116 }; 116 };
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