1 NXP LPC18xx/43xx DMA MUX (DMA request router) 1 NXP LPC18xx/43xx DMA MUX (DMA request router)
2 2
3 Required properties: 3 Required properties:
4 - compatible: "nxp,lpc1850-dmamux" 4 - compatible: "nxp,lpc1850-dmamux"
5 - reg: Memory map for accessing modul 5 - reg: Memory map for accessing module
6 - #dma-cells: Should be set to <3>. 6 - #dma-cells: Should be set to <3>.
7 * 1st cell contain the master 7 * 1st cell contain the master dma request signal
8 * 2nd cell contain the mux val 8 * 2nd cell contain the mux value (0-3) for the peripheral
9 * 3rd cell contain either 1 or 9 * 3rd cell contain either 1 or 2 depending on the AHB
10 master used. 10 master used.
11 - dma-requests: Number of DMA requests for the 11 - dma-requests: Number of DMA requests for the mux
12 - dma-masters: phandle pointing to the DMA co 12 - dma-masters: phandle pointing to the DMA controller
13 13
14 The DMA controller node need to have the follo 14 The DMA controller node need to have the following poroperties:
15 - dma-requests: Number of DMA requests the con 15 - dma-requests: Number of DMA requests the controller can handle
16 16
17 Example: 17 Example:
18 18
19 dmac: dma@40002000 { 19 dmac: dma@40002000 {
20 compatible = "nxp,lpc1850-gpdma", "arm 20 compatible = "nxp,lpc1850-gpdma", "arm,pl080", "arm,primecell";
21 arm,primecell-periphid = <0x00041080>; 21 arm,primecell-periphid = <0x00041080>;
22 reg = <0x40002000 0x1000>; 22 reg = <0x40002000 0x1000>;
23 interrupts = <2>; 23 interrupts = <2>;
24 clocks = <&ccu1 CLK_CPU_DMA>; 24 clocks = <&ccu1 CLK_CPU_DMA>;
25 clock-names = "apb_pclk"; 25 clock-names = "apb_pclk";
26 #dma-cells = <2>; 26 #dma-cells = <2>;
27 dma-channels = <8>; 27 dma-channels = <8>;
28 dma-requests = <16>; 28 dma-requests = <16>;
29 lli-bus-interface-ahb1; 29 lli-bus-interface-ahb1;
30 lli-bus-interface-ahb2; 30 lli-bus-interface-ahb2;
31 mem-bus-interface-ahb1; 31 mem-bus-interface-ahb1;
32 mem-bus-interface-ahb2; 32 mem-bus-interface-ahb2;
33 memcpy-burst-size = <256>; 33 memcpy-burst-size = <256>;
34 memcpy-bus-width = <32>; 34 memcpy-bus-width = <32>;
35 }; 35 };
36 36
37 dmamux: dma-mux { 37 dmamux: dma-mux {
38 compatible = "nxp,lpc1850-dmamux"; 38 compatible = "nxp,lpc1850-dmamux";
39 #dma-cells = <3>; 39 #dma-cells = <3>;
40 dma-requests = <64>; 40 dma-requests = <64>;
41 dma-masters = <&dmac>; 41 dma-masters = <&dmac>;
42 }; 42 };
43 43
44 uart0: serial@40081000 { 44 uart0: serial@40081000 {
45 compatible = "nxp,lpc1850-uart", "ns16 45 compatible = "nxp,lpc1850-uart", "ns16550a";
46 reg = <0x40081000 0x1000>; 46 reg = <0x40081000 0x1000>;
47 reg-shift = <2>; 47 reg-shift = <2>;
48 interrupts = <24>; 48 interrupts = <24>;
49 clocks = <&ccu2 CLK_APB0_UART0>, <&ccu 49 clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>;
50 clock-names = "uartclk", "reg"; 50 clock-names = "uartclk", "reg";
51 dmas = <&dmamux 1 1 2 51 dmas = <&dmamux 1 1 2
52 &dmamux 2 1 2>; 52 &dmamux 2 1 2>;
53 dma-names = "tx", "rx"; 53 dma-names = "tx", "rx";
54 }; 54 };
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