1 # SPDX-License-Identifier: GPL-2.0 1 # SPDX-License-Identifier: GPL-2.0
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/dma/owl-dma 4 $id: http://devicetree.org/schemas/dma/owl-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Actions Semi Owl SoCs DMA controller 7 title: Actions Semi Owl SoCs DMA controller
8 8
9 description: | 9 description: |
10 The OWL DMA is a general-purpose direct memo 10 The OWL DMA is a general-purpose direct memory access controller capable of
11 supporting 10 independent DMA channels for t 11 supporting 10 independent DMA channels for the Actions Semi S700 SoC and 12
12 independent DMA channels for the S500 and S9 12 independent DMA channels for the S500 and S900 SoC variants.
13 13
14 maintainers: 14 maintainers:
15 - Manivannan Sadhasivam <manivannan.sadhasiva 15 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
16 16
17 allOf: 17 allOf:
18 - $ref: dma-controller.yaml# 18 - $ref: dma-controller.yaml#
19 19
20 properties: 20 properties:
21 compatible: 21 compatible:
22 enum: 22 enum:
23 - actions,s500-dma 23 - actions,s500-dma
24 - actions,s700-dma 24 - actions,s700-dma
25 - actions,s900-dma 25 - actions,s900-dma
26 26
27 reg: 27 reg:
28 maxItems: 1 28 maxItems: 1
29 29
30 interrupts: 30 interrupts:
31 description: 31 description:
32 controller supports 4 interrupts, which 32 controller supports 4 interrupts, which are freely assignable to the
33 DMA channels. 33 DMA channels.
34 maxItems: 4 34 maxItems: 4
35 35
36 "#dma-cells": 36 "#dma-cells":
37 const: 1 37 const: 1
38 38
39 dma-channels: 39 dma-channels:
40 maximum: 12 40 maximum: 12
41 41
42 dma-requests: 42 dma-requests:
43 maximum: 46 43 maximum: 46
44 44
45 clocks: 45 clocks:
46 maxItems: 1 46 maxItems: 1
47 description: 47 description:
48 Phandle and Specifier of the clock feedi 48 Phandle and Specifier of the clock feeding the DMA controller.
49 49
50 power-domains: 50 power-domains:
51 maxItems: 1 51 maxItems: 1
52 52
53 required: 53 required:
54 - compatible 54 - compatible
55 - reg 55 - reg
56 - interrupts 56 - interrupts
57 - "#dma-cells" 57 - "#dma-cells"
58 - dma-channels 58 - dma-channels
59 - dma-requests 59 - dma-requests
60 - clocks 60 - clocks
61 61
62 unevaluatedProperties: false 62 unevaluatedProperties: false
63 63
64 examples: 64 examples:
65 - | 65 - |
66 #include <dt-bindings/interrupt-controller 66 #include <dt-bindings/interrupt-controller/arm-gic.h>
67 dma: dma-controller@e0260000 { 67 dma: dma-controller@e0260000 {
68 compatible = "actions,s900-dma"; 68 compatible = "actions,s900-dma";
69 reg = <0xe0260000 0x1000>; 69 reg = <0xe0260000 0x1000>;
70 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVE 70 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
71 <GIC_SPI 58 IRQ_TYPE_LEVE 71 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
72 <GIC_SPI 59 IRQ_TYPE_LEVE 72 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
73 <GIC_SPI 60 IRQ_TYPE_LEVE 73 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
74 #dma-cells = <1>; 74 #dma-cells = <1>;
75 dma-channels = <12>; 75 dma-channels = <12>;
76 dma-requests = <46>; 76 dma-requests = <46>;
77 clocks = <&clock 22>; 77 clocks = <&clock 22>;
78 }; 78 };
79 79
80 ... 80 ...
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