1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/dma/qcom,gp 4 $id: http://devicetree.org/schemas/dma/qcom,gpi.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Qualcomm Technologies Inc GPI DMA contr 7 title: Qualcomm Technologies Inc GPI DMA controller
8 8
9 maintainers: 9 maintainers:
10 - Vinod Koul <vkoul@kernel.org> 10 - Vinod Koul <vkoul@kernel.org>
11 11
12 description: | 12 description: |
13 QCOM GPI DMA controller provides DMA capabil 13 QCOM GPI DMA controller provides DMA capabilities for
14 peripheral buses such as I2C, UART, and SPI. 14 peripheral buses such as I2C, UART, and SPI.
15 15
16 allOf: 16 allOf:
17 - $ref: dma-controller.yaml# 17 - $ref: dma-controller.yaml#
18 18
19 properties: 19 properties:
20 compatible: 20 compatible:
21 oneOf: 21 oneOf:
22 - enum: 22 - enum:
23 - qcom,sdm845-gpi-dma 23 - qcom,sdm845-gpi-dma
24 - qcom,sm6350-gpi-dma 24 - qcom,sm6350-gpi-dma
25 - items: 25 - items:
26 - enum: 26 - enum:
27 - qcom,qcm2290-gpi-dma 27 - qcom,qcm2290-gpi-dma
28 - qcom,qdu1000-gpi-dma 28 - qcom,qdu1000-gpi-dma
29 - qcom,sc7280-gpi-dma 29 - qcom,sc7280-gpi-dma
30 - qcom,sdx75-gpi-dma <<
31 - qcom,sm6115-gpi-dma 30 - qcom,sm6115-gpi-dma
32 - qcom,sm6375-gpi-dma 31 - qcom,sm6375-gpi-dma
33 - qcom,sm8350-gpi-dma 32 - qcom,sm8350-gpi-dma
34 - qcom,sm8450-gpi-dma 33 - qcom,sm8450-gpi-dma
35 - qcom,sm8550-gpi-dma 34 - qcom,sm8550-gpi-dma
36 - qcom,sm8650-gpi-dma <<
37 - qcom,x1e80100-gpi-dma <<
38 - const: qcom,sm6350-gpi-dma 35 - const: qcom,sm6350-gpi-dma
39 - items: 36 - items:
40 - enum: 37 - enum:
41 - qcom,sdm670-gpi-dma 38 - qcom,sdm670-gpi-dma
42 - qcom,sm6125-gpi-dma 39 - qcom,sm6125-gpi-dma
43 - qcom,sm8150-gpi-dma 40 - qcom,sm8150-gpi-dma
44 - qcom,sm8250-gpi-dma 41 - qcom,sm8250-gpi-dma
45 - const: qcom,sdm845-gpi-dma 42 - const: qcom,sdm845-gpi-dma
46 43
47 reg: 44 reg:
48 maxItems: 1 45 maxItems: 1
49 46
50 interrupts: 47 interrupts:
51 description: 48 description:
52 Interrupt lines for each GPI instance 49 Interrupt lines for each GPI instance
53 minItems: 1 50 minItems: 1
54 maxItems: 13 51 maxItems: 13
55 52
56 "#dma-cells": 53 "#dma-cells":
57 const: 3 54 const: 3
58 description: > 55 description: >
59 DMA clients must use the format describe 56 DMA clients must use the format described in dma.txt, giving a phandle
60 to the DMA controller plus the following 57 to the DMA controller plus the following 3 integer cells:
61 - channel: if set to 0xffffffff, any ava 58 - channel: if set to 0xffffffff, any available channel will be allocated
62 for the client. Otherwise, the exact c 59 for the client. Otherwise, the exact channel specified will be used.
63 - seid: serial id of the client as defin 60 - seid: serial id of the client as defined in the SoC documentation.
64 - client: type of the client as defined 61 - client: type of the client as defined in dt-bindings/dma/qcom-gpi.h
65 62
66 iommus: 63 iommus:
67 maxItems: 1 64 maxItems: 1
68 65
69 dma-channels: 66 dma-channels:
70 maximum: 31 67 maximum: 31
71 68
72 dma-channel-mask: 69 dma-channel-mask:
73 maxItems: 1 70 maxItems: 1
74 <<
75 dma-coherent: true <<
76 71
77 required: 72 required:
78 - compatible 73 - compatible
79 - reg 74 - reg
80 - interrupts 75 - interrupts
81 - "#dma-cells" 76 - "#dma-cells"
82 - iommus 77 - iommus
83 - dma-channels 78 - dma-channels
84 - dma-channel-mask 79 - dma-channel-mask
85 80
86 additionalProperties: false 81 additionalProperties: false
87 82
88 examples: 83 examples:
89 - | 84 - |
90 #include <dt-bindings/interrupt-controller 85 #include <dt-bindings/interrupt-controller/arm-gic.h>
91 #include <dt-bindings/dma/qcom-gpi.h> 86 #include <dt-bindings/dma/qcom-gpi.h>
92 gpi_dma0: dma-controller@800000 { 87 gpi_dma0: dma-controller@800000 {
93 compatible = "qcom,sdm845-gpi-dma"; 88 compatible = "qcom,sdm845-gpi-dma";
94 #dma-cells = <3>; 89 #dma-cells = <3>;
95 reg = <0x00800000 0x60000>; 90 reg = <0x00800000 0x60000>;
96 iommus = <&apps_smmu 0x0016 0x0>; 91 iommus = <&apps_smmu 0x0016 0x0>;
97 dma-channels = <13>; 92 dma-channels = <13>;
98 dma-channel-mask = <0xfa>; 93 dma-channel-mask = <0xfa>;
99 interrupts = <GIC_SPI 244 IRQ_TYPE_LEV 94 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
100 <GIC_SPI 245 IRQ_TYPE_LEV 95 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
101 <GIC_SPI 246 IRQ_TYPE_LEV 96 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
102 <GIC_SPI 247 IRQ_TYPE_LEV 97 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 248 IRQ_TYPE_LEV 98 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 249 IRQ_TYPE_LEV 99 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 250 IRQ_TYPE_LEV 100 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 251 IRQ_TYPE_LEV 101 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 252 IRQ_TYPE_LEV 102 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
108 <GIC_SPI 253 IRQ_TYPE_LEV 103 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
109 <GIC_SPI 254 IRQ_TYPE_LEV 104 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
110 <GIC_SPI 255 IRQ_TYPE_LEV 105 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
111 <GIC_SPI 256 IRQ_TYPE_LEV 106 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
112 }; 107 };
113 108
114 ... 109 ...
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