1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-C 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/dma/sterics 4 $id: http://devicetree.org/schemas/dma/stericsson,dma40.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: ST-Ericsson DMA40 DMA Engine 7 title: ST-Ericsson DMA40 DMA Engine
8 8
9 maintainers: 9 maintainers:
10 - Linus Walleij <linus.walleij@linaro.org> 10 - Linus Walleij <linus.walleij@linaro.org>
11 11
12 allOf: 12 allOf:
13 - $ref: dma-controller.yaml# 13 - $ref: dma-controller.yaml#
14 14
15 properties: 15 properties:
16 "#dma-cells": 16 "#dma-cells":
17 const: 3 17 const: 3
18 description: | 18 description: |
19 The first cell is the unique device chan 19 The first cell is the unique device channel number as indicated by this
20 table for DB8500 which is the only ASIC 20 table for DB8500 which is the only ASIC known to use DMA40:
21 21
22 0: SPI controller 0 22 0: SPI controller 0
23 1: SD/MMC controller 0 (unused) 23 1: SD/MMC controller 0 (unused)
24 2: SD/MMC controller 1 (unused) 24 2: SD/MMC controller 1 (unused)
25 3: SD/MMC controller 2 (unused) 25 3: SD/MMC controller 2 (unused)
26 4: I2C port 1 26 4: I2C port 1
27 5: I2C port 3 27 5: I2C port 3
28 6: I2C port 2 28 6: I2C port 2
29 7: I2C port 4 29 7: I2C port 4
30 8: Synchronous Serial Port SSP0 30 8: Synchronous Serial Port SSP0
31 9: Synchronous Serial Port SSP1 31 9: Synchronous Serial Port SSP1
32 10: Multi-Channel Display Engine MCDE RX 32 10: Multi-Channel Display Engine MCDE RX
33 11: UART port 2 33 11: UART port 2
34 12: UART port 1 34 12: UART port 1
35 13: UART port 0 35 13: UART port 0
36 14: Multirate Serial Port MSP2 36 14: Multirate Serial Port MSP2
37 15: I2C port 0 37 15: I2C port 0
38 16: USB OTG in/out endpoints 7 & 15 38 16: USB OTG in/out endpoints 7 & 15
39 17: USB OTG in/out endpoints 6 & 14 39 17: USB OTG in/out endpoints 6 & 14
40 18: USB OTG in/out endpoints 5 & 13 40 18: USB OTG in/out endpoints 5 & 13
41 19: USB OTG in/out endpoints 4 & 12 41 19: USB OTG in/out endpoints 4 & 12
42 20: SLIMbus or HSI channel 0 42 20: SLIMbus or HSI channel 0
43 21: SLIMbus or HSI channel 1 43 21: SLIMbus or HSI channel 1
44 22: SLIMbus or HSI channel 2 44 22: SLIMbus or HSI channel 2
45 23: SLIMbus or HSI channel 3 45 23: SLIMbus or HSI channel 3
46 24: Multimedia DSP SXA0 46 24: Multimedia DSP SXA0
47 25: Multimedia DSP SXA1 47 25: Multimedia DSP SXA1
48 26: Multimedia DSP SXA2 48 26: Multimedia DSP SXA2
49 27: Multimedia DSP SXA3 49 27: Multimedia DSP SXA3
50 28: SD/MMC controller 2 50 28: SD/MMC controller 2
51 29: SD/MMC controller 0 51 29: SD/MMC controller 0
52 30: MSP port 1 on DB8500 v1, MSP port 3 52 30: MSP port 1 on DB8500 v1, MSP port 3 on DB8500 v2
53 31: MSP port 0 or SLIMbus channel 0 53 31: MSP port 0 or SLIMbus channel 0
54 32: SD/MMC controller 1 54 32: SD/MMC controller 1
55 33: SPI controller 2 55 33: SPI controller 2
56 34: i2c3 RX2 TX2 56 34: i2c3 RX2 TX2
57 35: SPI controller 1 57 35: SPI controller 1
58 36: USB OTG in/out endpoints 3 & 11 58 36: USB OTG in/out endpoints 3 & 11
59 37: USB OTG in/out endpoints 2 & 10 59 37: USB OTG in/out endpoints 2 & 10
60 38: USB OTG in/out endpoints 1 & 9 60 38: USB OTG in/out endpoints 1 & 9
61 39: USB OTG in/out endpoints 8 61 39: USB OTG in/out endpoints 8
62 40: SPI controller 3 62 40: SPI controller 3
63 41: SD/MMC controller 3 63 41: SD/MMC controller 3
64 42: SD/MMC controller 4 64 42: SD/MMC controller 4
65 43: SD/MMC controller 5 65 43: SD/MMC controller 5
66 44: Multimedia DSP SXA4 66 44: Multimedia DSP SXA4
67 45: Multimedia DSP SXA5 67 45: Multimedia DSP SXA5
68 46: SLIMbus channel 8 or Multimedia DSP 68 46: SLIMbus channel 8 or Multimedia DSP SXA6
69 47: SLIMbus channel 9 or Multimedia DSP 69 47: SLIMbus channel 9 or Multimedia DSP SXA7
70 48: Crypto Accelerator 1 70 48: Crypto Accelerator 1
71 49: Crypto Accelerator 1 TX or Hash Acce 71 49: Crypto Accelerator 1 TX or Hash Accelerator 1 TX
72 50: Hash Accelerator 1 TX 72 50: Hash Accelerator 1 TX
73 51: memcpy TX (to be used by the DMA dri 73 51: memcpy TX (to be used by the DMA driver for memcpy operations)
74 52: SLIMbus or HSI channel 4 74 52: SLIMbus or HSI channel 4
75 53: SLIMbus or HSI channel 5 75 53: SLIMbus or HSI channel 5
76 54: SLIMbus or HSI channel 6 76 54: SLIMbus or HSI channel 6
77 55: SLIMbus or HSI channel 7 77 55: SLIMbus or HSI channel 7
78 56: memcpy (to be used by the DMA driver 78 56: memcpy (to be used by the DMA driver for memcpy operations)
79 57: memcpy (to be used by the DMA driver 79 57: memcpy (to be used by the DMA driver for memcpy operations)
80 58: memcpy (to be used by the DMA driver 80 58: memcpy (to be used by the DMA driver for memcpy operations)
81 59: memcpy (to be used by the DMA driver 81 59: memcpy (to be used by the DMA driver for memcpy operations)
82 60: memcpy (to be used by the DMA driver 82 60: memcpy (to be used by the DMA driver for memcpy operations)
83 61: Crypto Accelerator 0 83 61: Crypto Accelerator 0
84 62: Crypto Accelerator 0 TX or Hash Acce 84 62: Crypto Accelerator 0 TX or Hash Accelerator 0 TX
85 63: Hash Accelerator 0 TX 85 63: Hash Accelerator 0 TX
86 86
87 The second cell is the DMA request line 87 The second cell is the DMA request line number. This is only used when
88 a fixed channel is allocated, and indica 88 a fixed channel is allocated, and indicated by setting bit 3 in the
89 flags field (see below). 89 flags field (see below).
90 90
91 The third cell is a 32bit flags bitfield 91 The third cell is a 32bit flags bitfield with the following possible
92 bits set: 92 bits set:
93 0x00000001 (bit 0) - mode: 93 0x00000001 (bit 0) - mode:
94 Logical channel when unset 94 Logical channel when unset
95 Physical channel when set 95 Physical channel when set
96 0x00000002 (bit 1) - direction: 96 0x00000002 (bit 1) - direction:
97 Memory to Device when unset 97 Memory to Device when unset
98 Device to Memory when set 98 Device to Memory when set
99 0x00000004 (bit 2) - endianness: 99 0x00000004 (bit 2) - endianness:
100 Little endian when unset 100 Little endian when unset
101 Big endian when set 101 Big endian when set
102 0x00000008 (bit 3) - use fixed channel: 102 0x00000008 (bit 3) - use fixed channel:
103 Use automatic channel selection when u 103 Use automatic channel selection when unset
104 Use DMA request line number when set 104 Use DMA request line number when set
105 0x00000010 (bit 4) - set channel as high 105 0x00000010 (bit 4) - set channel as high priority:
106 Normal priority when unset 106 Normal priority when unset
107 High priority when set 107 High priority when set
108 108
109 compatible: 109 compatible:
110 items: 110 items:
111 - const: stericsson,db8500-dma40 111 - const: stericsson,db8500-dma40
112 - const: stericsson,dma40 112 - const: stericsson,dma40
113 113
114 reg: 114 reg:
115 oneOf: 115 oneOf:
116 - items: 116 - items:
117 - description: DMA40 memory base 117 - description: DMA40 memory base
118 - items: 118 - items:
119 - description: DMA40 memory base 119 - description: DMA40 memory base
120 - description: LCPA memory base, dep 120 - description: LCPA memory base, deprecated, use eSRAM pool instead
121 deprecated: true 121 deprecated: true
122 122
123 123
124 reg-names: 124 reg-names:
125 oneOf: 125 oneOf:
126 - items: 126 - items:
127 - const: base 127 - const: base
128 - items: 128 - items:
129 - const: base 129 - const: base
130 - const: lcpa 130 - const: lcpa
131 deprecated: true 131 deprecated: true
132 132
133 interrupts: 133 interrupts:
134 maxItems: 1 134 maxItems: 1
135 135
136 clocks: 136 clocks:
137 maxItems: 1 137 maxItems: 1
138 138
139 sram: 139 sram:
140 $ref: /schemas/types.yaml#/definitions/pha 140 $ref: /schemas/types.yaml#/definitions/phandle-array
141 description: A phandle array with inner si 141 description: A phandle array with inner size 1 (no arg cells).
142 First phandle is the LCPA (Logical Chann 142 First phandle is the LCPA (Logical Channel Parameter Address) memory.
143 Second phandle is the LCLA (Logical Cha 143 Second phandle is the LCLA (Logical Channel Link base Address) memory.
144 maxItems: 2 144 maxItems: 2
145 items: 145 items:
146 maxItems: 1 146 maxItems: 1
147 147
148 memcpy-channels: 148 memcpy-channels:
149 $ref: /schemas/types.yaml#/definitions/uin 149 $ref: /schemas/types.yaml#/definitions/uint32-array
150 description: Array of u32 elements indicat 150 description: Array of u32 elements indicating which channels on the DMA
151 engine are eligible for memcpy transfers 151 engine are eligible for memcpy transfers
152 152
153 required: 153 required:
154 - "#dma-cells" 154 - "#dma-cells"
155 - compatible 155 - compatible
156 - reg 156 - reg
157 - interrupts 157 - interrupts
158 - clocks 158 - clocks
159 - sram 159 - sram
160 - memcpy-channels 160 - memcpy-channels
161 161
162 additionalProperties: false 162 additionalProperties: false
163 163
164 examples: 164 examples:
165 - | 165 - |
166 #include <dt-bindings/interrupt-controller 166 #include <dt-bindings/interrupt-controller/irq.h>
167 #include <dt-bindings/interrupt-controller 167 #include <dt-bindings/interrupt-controller/arm-gic.h>
168 #include <dt-bindings/mfd/dbx500-prcmu.h> 168 #include <dt-bindings/mfd/dbx500-prcmu.h>
169 dma-controller@801c0000 { 169 dma-controller@801c0000 {
170 compatible = "stericsson,db8500-dma40" 170 compatible = "stericsson,db8500-dma40", "stericsson,dma40";
171 reg = <0x801c0000 0x1000>; 171 reg = <0x801c0000 0x1000>;
172 reg-names = "base"; 172 reg-names = "base";
173 sram = <&lcpa>, <&lcla>; 173 sram = <&lcpa>, <&lcla>;
174 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVE 174 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
175 #dma-cells = <3>; 175 #dma-cells = <3>;
176 memcpy-channels = <56 57 58 59 60>; 176 memcpy-channels = <56 57 58 59 60>;
177 clocks = <&prcmu_clk PRCMU_DMACLK>; 177 clocks = <&prcmu_clk PRCMU_DMACLK>;
178 }; 178 };
179 ... 179 ...
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