1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/dma/xilinx/ 4 $id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Xilinx ZynqMP DMA Engine 7 title: Xilinx ZynqMP DMA Engine
8 8
9 description: | 9 description: |
10 The Xilinx ZynqMP DMA engine supports memory 10 The Xilinx ZynqMP DMA engine supports memory to memory transfers,
11 memory to device and device to memory transf 11 memory to device and device to memory transfers. It also has flow
12 control and rate control support for slave/p 12 control and rate control support for slave/peripheral dma access.
13 13
14 maintainers: 14 maintainers:
15 - Michael Tretter <m.tretter@pengutronix.de> 15 - Michael Tretter <m.tretter@pengutronix.de>
16 - Harini Katakam <harini.katakam@amd.com> 16 - Harini Katakam <harini.katakam@amd.com>
17 - Radhey Shyam Pandey <radhey.shyam.pandey@am 17 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
18 18
19 allOf: 19 allOf:
20 - $ref: ../dma-controller.yaml# 20 - $ref: ../dma-controller.yaml#
21 21
22 properties: 22 properties:
23 "#dma-cells": 23 "#dma-cells":
24 const: 1 24 const: 1
25 25
26 compatible: 26 compatible:
27 enum: 27 enum:
28 - amd,versal2-dma-1.0 28 - amd,versal2-dma-1.0
29 - xlnx,zynqmp-dma-1.0 29 - xlnx,zynqmp-dma-1.0
30 30
31 reg: 31 reg:
32 description: memory map for gdma/adma modu 32 description: memory map for gdma/adma module access
33 maxItems: 1 33 maxItems: 1
34 34
35 interrupts: 35 interrupts:
36 description: DMA channel interrupt 36 description: DMA channel interrupt
37 maxItems: 1 37 maxItems: 1
38 38
39 clocks: 39 clocks:
40 description: input clocks 40 description: input clocks
41 minItems: 2 41 minItems: 2
42 maxItems: 2 42 maxItems: 2
43 43
44 clock-names: 44 clock-names:
45 items: 45 items:
46 - const: clk_main 46 - const: clk_main
47 - const: clk_apb 47 - const: clk_apb
48 48
49 xlnx,bus-width: 49 xlnx,bus-width:
50 $ref: /schemas/types.yaml#/definitions/uin 50 $ref: /schemas/types.yaml#/definitions/uint32
51 enum: 51 enum:
52 - 64 52 - 64
53 - 128 53 - 128
54 description: AXI bus width in bits 54 description: AXI bus width in bits
55 55
56 iommus: 56 iommus:
57 maxItems: 1 57 maxItems: 1
58 58
59 power-domains: 59 power-domains:
60 maxItems: 1 60 maxItems: 1
61 61
62 dma-coherent: 62 dma-coherent:
63 description: present if dma operations are 63 description: present if dma operations are coherent
64 64
65 required: 65 required:
66 - "#dma-cells" 66 - "#dma-cells"
67 - compatible 67 - compatible
68 - reg 68 - reg
69 - interrupts 69 - interrupts
70 - clocks 70 - clocks
71 - clock-names 71 - clock-names
72 - xlnx,bus-width 72 - xlnx,bus-width
73 73
74 additionalProperties: false 74 additionalProperties: false
75 75
76 examples: 76 examples:
77 - | 77 - |
78 #include <dt-bindings/clock/xlnx-zynqmp-cl 78 #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
79 79
80 fpd_dma_chan1: dma-controller@fd500000 { 80 fpd_dma_chan1: dma-controller@fd500000 {
81 compatible = "xlnx,zynqmp-dma-1.0"; 81 compatible = "xlnx,zynqmp-dma-1.0";
82 reg = <0xfd500000 0x1000>; 82 reg = <0xfd500000 0x1000>;
83 interrupt-parent = <&gic>; 83 interrupt-parent = <&gic>;
84 interrupts = <0 117 0x4>; 84 interrupts = <0 117 0x4>;
85 #dma-cells = <1>; 85 #dma-cells = <1>;
86 clock-names = "clk_main", "clk_apb"; 86 clock-names = "clk_main", "clk_apb";
87 clocks = <&zynqmp_clk GDMA_REF>, <&zynqm 87 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
88 xlnx,bus-width = <128>; 88 xlnx,bus-width = <128>;
89 dma-coherent; 89 dma-coherent;
90 }; 90 };
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