1 Aspeed BMC SoC EDAC node 1 Aspeed BMC SoC EDAC node
2 2
3 The Aspeed BMC SoC supports DDR3 and DDR4 memo 3 The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error
4 correction check). 4 correction check).
5 5
6 The memory controller supports SECDED (single 6 The memory controller supports SECDED (single bit error correction, double bit
7 error detection) and single bit error auto scr 7 error detection) and single bit error auto scrubbing by reserving 8 bits for
8 every 64 bit word (effectively reducing availa 8 every 64 bit word (effectively reducing available memory to 8/9).
9 9
10 Note, the bootloader must configure ECC mode i 10 Note, the bootloader must configure ECC mode in the memory controller.
11 11
12 12
13 Required properties: 13 Required properties:
14 - compatible: should be one of 14 - compatible: should be one of
15 - "aspeed,ast2400-sdram-edac" 15 - "aspeed,ast2400-sdram-edac"
16 - "aspeed,ast2500-sdram-edac" 16 - "aspeed,ast2500-sdram-edac"
17 - "aspeed,ast2600-sdram-edac" 17 - "aspeed,ast2600-sdram-edac"
18 - reg: sdram controller register set sh 18 - reg: sdram controller register set should be <0x1e6e0000 0x174>
19 - interrupts: should be AVIC interrupt #0 19 - interrupts: should be AVIC interrupt #0
20 20
21 21
22 Example: 22 Example:
23 23
24 edac: sdram@1e6e0000 { 24 edac: sdram@1e6e0000 {
25 compatible = "aspeed,ast2500-s 25 compatible = "aspeed,ast2500-sdram-edac";
26 reg = <0x1e6e0000 0x174>; 26 reg = <0x1e6e0000 0x174>;
27 interrupts = <0>; 27 interrupts = <0>;
28 }; 28 };
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