1 Intel Service Layer Driver for Stratix10 SoC 1 Intel Service Layer Driver for Stratix10 SoC
2 ============================================ 2 ============================================
3 Intel Stratix10 SoC is composed of a 64 bit qu 3 Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard
4 processor system (HPS) and Secure Device Manag 4 processor system (HPS) and Secure Device Manager (SDM). When the FPGA is
5 configured from HPS, there needs to be a way f 5 configured from HPS, there needs to be a way for HPS to notify SDM the
6 location and size of the configuration data. T 6 location and size of the configuration data. Then SDM will get the
7 configuration data from that location and perf 7 configuration data from that location and perform the FPGA configuration.
8 8
9 To meet the whole system security needs and su 9 To meet the whole system security needs and support virtual machine requesting
10 communication with SDM, only the secure world 10 communication with SDM, only the secure world of software (EL3, Exception
11 Layer 3) can interface with SDM. All software 11 Layer 3) can interface with SDM. All software entities running on other
12 exception layers must channel through the EL3 12 exception layers must channel through the EL3 software whenever it needs
13 service from SDM. 13 service from SDM.
14 14
15 Intel Stratix10 service layer driver, running 15 Intel Stratix10 service layer driver, running at privileged exception level
16 (EL1, Exception Layer 1), interfaces with the 16 (EL1, Exception Layer 1), interfaces with the service providers and provides
17 the services for FPGA configuration, QSPI, Cry 17 the services for FPGA configuration, QSPI, Crypto and warm reset. Service layer
18 driver also manages secure monitor call (SMC) 18 driver also manages secure monitor call (SMC) to communicate with secure monitor
19 code running in EL3. 19 code running in EL3.
20 20
21 Required properties: 21 Required properties:
22 ------------------- 22 -------------------
23 The svc node has the following mandatory prope 23 The svc node has the following mandatory properties, must be located under
24 the firmware node. 24 the firmware node.
25 25
26 - compatible: "intel,stratix10-svc" or "intel, 26 - compatible: "intel,stratix10-svc" or "intel,agilex-svc"
27 - method: smc or hvc 27 - method: smc or hvc
28 smc - Secure Monitor Call 28 smc - Secure Monitor Call
29 hvc - Hypervisor Call 29 hvc - Hypervisor Call
30 - memory-region: 30 - memory-region:
31 phandle to the reserved memory node. S 31 phandle to the reserved memory node. See
32 Documentation/devicetree/bindings/rese 32 Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
33 for details 33 for details
34 34
35 Example: 35 Example:
36 ------- 36 -------
37 37
38 reserved-memory { 38 reserved-memory {
39 #address-cells = <2>; 39 #address-cells = <2>;
40 #size-cells = <2>; 40 #size-cells = <2>;
41 ranges; 41 ranges;
42 42
43 service_reserved: svcbuffer@0 43 service_reserved: svcbuffer@0 {
44 compatible = "shared-d 44 compatible = "shared-dma-pool";
45 reg = <0x0 0x0 0x0 0x1 45 reg = <0x0 0x0 0x0 0x1000000>;
46 alignment = <0x1000>; 46 alignment = <0x1000>;
47 no-map; 47 no-map;
48 }; 48 };
49 }; 49 };
50 50
51 firmware { 51 firmware {
52 svc { 52 svc {
53 compatible = "intel,st 53 compatible = "intel,stratix10-svc";
54 method = "smc"; 54 method = "smc";
55 memory-region = <&serv 55 memory-region = <&service_reserved>;
56 }; 56 };
57 }; 57 };
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