1 NVIDIA Tegra210 Boot and Power Management Proc 1 NVIDIA Tegra210 Boot and Power Management Processor (BPMP)
2 2
3 The Boot and Power Management Processor (BPMP) 3 The Boot and Power Management Processor (BPMP) is a co-processor found
4 in Tegra210 SoC. It is designed to handle the 4 in Tegra210 SoC. It is designed to handle the early stages of the boot
5 process as well as to assisting in entering de 5 process as well as to assisting in entering deep low power state
6 (suspend to ram), and also offloading DRAM mem 6 (suspend to ram), and also offloading DRAM memory clock scaling on
7 some platforms. The binding document defines t 7 some platforms. The binding document defines the resources that would
8 be used by the BPMP T210 firmware driver, whic 8 be used by the BPMP T210 firmware driver, which can create the
9 interprocessor communication (IPC) between the 9 interprocessor communication (IPC) between the CPU and BPMP.
10 10
11 Required properties: 11 Required properties:
12 - compatible 12 - compatible
13 Array of strings 13 Array of strings
14 One of: 14 One of:
15 - "nvidia,tegra210-bpmp" 15 - "nvidia,tegra210-bpmp"
16 - reg: physical base address and length for HW 16 - reg: physical base address and length for HW synchornization primitives
17 1) base address and length to Tegra 'at 17 1) base address and length to Tegra 'atomics' hardware
18 2) base address and length to Tegra 'se 18 2) base address and length to Tegra 'semaphore' hardware
19 - interrupts: specifies the interrupt number f 19 - interrupts: specifies the interrupt number for receiving messages ("rx")
20 and for triggering messages ("tx 20 and for triggering messages ("tx")
21 21
22 Optional properties: 22 Optional properties:
23 - #clock-cells : Should be 1 for platforms whe 23 - #clock-cells : Should be 1 for platforms where DRAM clock control is
24 offloaded to bpmp. 24 offloaded to bpmp.
25 25
26 Example: 26 Example:
27 27
28 bpmp@70016000 { 28 bpmp@70016000 {
29 compatible = "nvidia,tegra210-bpmp"; 29 compatible = "nvidia,tegra210-bpmp";
30 reg = <0x0 0x70016000 0x0 0x2000 30 reg = <0x0 0x70016000 0x0 0x2000
31 0x0 0x60001000 0x0 0x1000>; 31 0x0 0x60001000 0x0 0x1000>;
32 interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_ 32 interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>,
33 <GIC_SPI 4 IRQ_TYPE_EDGE_ 33 <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
34 interrupt-names = "tx", "rx"; 34 interrupt-names = "tx", "rx";
35 }; 35 };
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