1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/firmware/xi 4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Xilinx firmware driver 7 title: Xilinx firmware driver
8 8
9 maintainers: 9 maintainers:
10 - Nava kishore Manne <nava.kishore.manne@amd. 10 - Nava kishore Manne <nava.kishore.manne@amd.com>
11 11
12 description: The zynqmp-firmware node describe 12 description: The zynqmp-firmware node describes the interface to platform
13 firmware. ZynqMP has an interface to communi 13 firmware. ZynqMP has an interface to communicate with secure firmware.
14 Firmware driver provides an interface to fir 14 Firmware driver provides an interface to firmware APIs. Interface APIs
15 can be used by any driver to communicate to 15 can be used by any driver to communicate to PMUFW(Platform Management Unit).
16 These requests include clock management, pin 16 These requests include clock management, pin control, device control,
17 power management service, FPGA service and o 17 power management service, FPGA service and other platform management
18 services. 18 services.
19 19
20 properties: 20 properties:
21 compatible: 21 compatible:
22 oneOf: 22 oneOf:
23 - description: For implementations compl 23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.
24 const: xlnx,zynqmp-firmware 24 const: xlnx,zynqmp-firmware
25 25
26 - description: For implementations compl 26 - description: For implementations complying for Versal.
27 const: xlnx,versal-firmware 27 const: xlnx,versal-firmware
28 28
29 - description: For implementations compl 29 - description: For implementations complying for Versal NET.
30 items: 30 items:
31 - enum: 31 - enum:
32 - xlnx,versal-net-firmware 32 - xlnx,versal-net-firmware
33 - const: xlnx,versal-firmware 33 - const: xlnx,versal-firmware
34 34
35 method: 35 method:
36 description: | 36 description: |
37 The method of calling the PM- 37 The method of calling the PM-API firmware layer.
38 Permitted values are. 38 Permitted values are.
39 - "smc" : SMC #0, following t 39 - "smc" : SMC #0, following the SMCCC
40 - "hvc" : HVC #0, following t 40 - "hvc" : HVC #0, following the SMCCC
41 41
42 $ref: /schemas/types.yaml#/definitions/str 42 $ref: /schemas/types.yaml#/definitions/string-array
43 enum: 43 enum:
44 - smc 44 - smc
45 - hvc 45 - hvc
46 46
47 "#power-domain-cells": 47 "#power-domain-cells":
48 const: 1 48 const: 1
49 49
50 clock-controller: 50 clock-controller:
51 $ref: /schemas/clock/xlnx,versal-clk.yaml# 51 $ref: /schemas/clock/xlnx,versal-clk.yaml#
52 description: The clock controller is a har 52 description: The clock controller is a hardware block of Xilinx versal
53 clock tree. It reads required input cloc 53 clock tree. It reads required input clock frequencies from the devicetree
54 and acts as clock provider for all clock 54 and acts as clock provider for all clock consumers of PS clocks.list of
55 clock specifiers which are external inpu 55 clock specifiers which are external input clocks to the given clock
56 controller. 56 controller.
57 type: object 57 type: object
58 58
59 gpio: 59 gpio:
60 $ref: /schemas/gpio/xlnx,zynqmp-gpio-modep 60 $ref: /schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml#
61 description: The gpio node describes conne 61 description: The gpio node describes connect to PS_MODE pins via firmware
62 interface. 62 interface.
63 type: object 63 type: object
64 64
65 soc-nvmem: 65 soc-nvmem:
66 $ref: /schemas/nvmem/xlnx,zynqmp-nvmem.yam 66 $ref: /schemas/nvmem/xlnx,zynqmp-nvmem.yaml#
67 description: The ZynqMP MPSoC provides acc 67 description: The ZynqMP MPSoC provides access to the hardware related data
68 like SOC revision, IDCODE and specific p 68 like SOC revision, IDCODE and specific purpose efuses.
69 type: object 69 type: object
70 70
71 pcap: 71 pcap:
72 $ref: /schemas/fpga/xlnx,zynqmp-pcap-fpga. 72 $ref: /schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml
73 description: The ZynqMP SoC uses the PCAP 73 description: The ZynqMP SoC uses the PCAP (Processor Configuration Port) to
74 configure the Programmable Logic (PL). T 74 configure the Programmable Logic (PL). The configuration uses the
75 firmware interface. 75 firmware interface.
76 type: object 76 type: object
77 77
78 pinctrl: 78 pinctrl:
79 $ref: /schemas/pinctrl/xlnx,zynqmp-pinctrl 79 $ref: /schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml#
80 description: The pinctrl node provides acc 80 description: The pinctrl node provides access to pinconfig and pincontrol
81 functionality available in firmware. 81 functionality available in firmware.
82 type: object 82 type: object
83 83
84 power-management: 84 power-management:
85 $ref: /schemas/power/reset/xlnx,zynqmp-pow 85 $ref: /schemas/power/reset/xlnx,zynqmp-power.yaml#
86 description: The zynqmp-power node describ 86 description: The zynqmp-power node describes the power management
87 configurations. It will control remote s 87 configurations. It will control remote suspend/shutdown interfaces.
88 type: object 88 type: object
89 89
90 reset-controller: 90 reset-controller:
91 $ref: /schemas/reset/xlnx,zynqmp-reset.yam 91 $ref: /schemas/reset/xlnx,zynqmp-reset.yaml#
92 description: The reset-controller node des 92 description: The reset-controller node describes connection to the reset
93 functionality via firmware interface. 93 functionality via firmware interface.
94 type: object 94 type: object
95 95
96 versal-fpga: 96 versal-fpga:
97 $ref: /schemas/fpga/xlnx,versal-fpga.yaml# 97 $ref: /schemas/fpga/xlnx,versal-fpga.yaml#
98 description: Compatible of the FPGA device 98 description: Compatible of the FPGA device.
99 type: object 99 type: object
100 100
101 zynqmp-aes: 101 zynqmp-aes:
102 $ref: /schemas/crypto/xlnx,zynqmp-aes.yaml 102 $ref: /schemas/crypto/xlnx,zynqmp-aes.yaml#
103 description: The ZynqMP AES-GCM hardened c 103 description: The ZynqMP AES-GCM hardened cryptographic accelerator is
104 used to encrypt or decrypt the data with 104 used to encrypt or decrypt the data with provided key and initialization
105 vector. 105 vector.
106 type: object 106 type: object
107 107
108 required: 108 required:
109 - compatible 109 - compatible
110 110
111 additionalProperties: false 111 additionalProperties: false
112 112
113 examples: 113 examples:
114 - | 114 - |
115 #include <dt-bindings/power/xlnx-zynqmp-po 115 #include <dt-bindings/power/xlnx-zynqmp-power.h>
116 firmware { 116 firmware {
117 zynqmp_firmware: zynqmp-firmware { 117 zynqmp_firmware: zynqmp-firmware {
118 #power-domain-cells = <1>; 118 #power-domain-cells = <1>;
119 soc-nvmem { 119 soc-nvmem {
120 compatible = "xlnx,zynqmp-nvmem-fw"; 120 compatible = "xlnx,zynqmp-nvmem-fw";
121 nvmem-layout { 121 nvmem-layout {
122 compatible = "fixed-layout"; 122 compatible = "fixed-layout";
123 #address-cells = <1>; 123 #address-cells = <1>;
124 #size-cells = <1>; 124 #size-cells = <1>;
125 125
126 soc_revision: soc-revision@0 { 126 soc_revision: soc-revision@0 {
127 reg = <0x0 0x4>; 127 reg = <0x0 0x4>;
128 }; 128 };
129 }; 129 };
130 }; 130 };
131 gpio { 131 gpio {
132 compatible = "xlnx,zynqmp-gpio-modep 132 compatible = "xlnx,zynqmp-gpio-modepin";
133 gpio-controller; 133 gpio-controller;
134 #gpio-cells = <2>; 134 #gpio-cells = <2>;
135 }; 135 };
136 pcap { 136 pcap {
137 compatible = "xlnx,zynqmp-pcap-fpga" 137 compatible = "xlnx,zynqmp-pcap-fpga";
138 }; 138 };
139 pinctrl { 139 pinctrl {
140 compatible = "xlnx,zynqmp-pinctrl"; 140 compatible = "xlnx,zynqmp-pinctrl";
141 }; 141 };
142 power-management { 142 power-management {
143 compatible = "xlnx,zynqmp-power"; 143 compatible = "xlnx,zynqmp-power";
144 interrupts = <0 35 4>; 144 interrupts = <0 35 4>;
145 }; 145 };
146 reset-controller { 146 reset-controller {
147 compatible = "xlnx,zynqmp-reset"; 147 compatible = "xlnx,zynqmp-reset";
148 #reset-cells = <1>; 148 #reset-cells = <1>;
149 }; 149 };
150 }; 150 };
151 }; 151 };
152 152
153 sata { 153 sata {
154 power-domains = <&zynqmp_firmware PD_SAT 154 power-domains = <&zynqmp_firmware PD_SATA>;
155 }; 155 };
156 156
157 versal-firmware { 157 versal-firmware {
158 compatible = "xlnx,versal-firmware"; 158 compatible = "xlnx,versal-firmware";
159 method = "smc"; 159 method = "smc";
160 160
161 versal_fpga: versal-fpga { 161 versal_fpga: versal-fpga {
162 compatible = "xlnx,versal-fpga"; 162 compatible = "xlnx,versal-fpga";
163 }; 163 };
164 164
165 xlnx_aes: zynqmp-aes { 165 xlnx_aes: zynqmp-aes {
166 compatible = "xlnx,zynqmp-aes"; 166 compatible = "xlnx,zynqmp-aes";
167 }; 167 };
168 168
169 versal_clk: clock-controller { 169 versal_clk: clock-controller {
170 #clock-cells = <1>; 170 #clock-cells = <1>;
171 compatible = "xlnx,versal-clk"; 171 compatible = "xlnx,versal-clk";
172 clocks = <&ref>, <&pl_alt_ref>; 172 clocks = <&ref>, <&pl_alt_ref>;
173 clock-names = "ref", "pl_alt_ref"; 173 clock-names = "ref", "pl_alt_ref";
174 }; 174 };
175 }; 175 };
176 176
177 ... 177 ...
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