1 Lattice iCE40 FPGA Manager 1 Lattice iCE40 FPGA Manager
2 2
3 Required properties: 3 Required properties:
4 - compatible: Should contain "lattic 4 - compatible: Should contain "lattice,ice40-fpga-mgr"
5 - reg: SPI chip select 5 - reg: SPI chip select
6 - spi-max-frequency: Maximum SPI frequency 6 - spi-max-frequency: Maximum SPI frequency (>=1000000, <=25000000)
7 - cdone-gpios: GPIO input connected t 7 - cdone-gpios: GPIO input connected to CDONE pin
8 - reset-gpios: Active-low GPIO output 8 - reset-gpios: Active-low GPIO output connected to CRESET_B pin. Note
9 that unless the GPIO i 9 that unless the GPIO is held low during startup, the
10 FPGA will enter Master 10 FPGA will enter Master SPI mode and drive SCK with a
11 clock signal potential 11 clock signal potentially jamming other devices on the
12 bus until the firmware 12 bus until the firmware is loaded.
13 13
14 Example: 14 Example:
15 fpga: fpga@0 { 15 fpga: fpga@0 {
16 compatible = "lattice,ice40-fp 16 compatible = "lattice,ice40-fpga-mgr";
17 reg = <0>; 17 reg = <0>;
18 spi-max-frequency = <1000000>; 18 spi-max-frequency = <1000000>;
19 cdone-gpios = <&gpio 24 GPIO_A 19 cdone-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
20 reset-gpios = <&gpio 22 GPIO_A 20 reset-gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
21 }; 21 };
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