1 # SPDX-License-Identifier: (GPL-2.0-only OR BS
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,p
5 $schema: http://devicetree.org/meta-schemas/co
6
7 title: Xilinx LogiCORE Partial Reconfig Decoup
8
9 maintainers:
10 - Nava kishore Manne <nava.kishore.manne@amd.
11
12 allOf:
13 - $ref: fpga-bridge.yaml#
14
15 description: |
16 The Xilinx LogiCORE Partial Reconfig(PR) Dec
17 decouplers/fpga bridges. The controller can
18 which prevents signal changes from passing t
19 can also couple / enable the bridges which a
20 bridge normally.
21 Xilinx LogiCORE Dynamic Function eXchange(DF
22 is compatible with the Xilinx LogiCORE pr-de
23 eXchange AXI shutdown manager prevents AXI t
24 bridge. The controller safely handles AXI4MM
25 Reconfigurable Partition when it is undergoi
26 preventing the system deadlock that can occu
27 interrupted by DFX.
28 Please refer to fpga-region.txt and fpga-bri
29 common binding part and usage.
30
31 properties:
32 compatible:
33 oneOf:
34 - items:
35 - const: xlnx,pr-decoupler-1.00
36 - const: xlnx,pr-decoupler
37 - items:
38 - const: xlnx,dfx-axi-shutdown-manag
39 - const: xlnx,dfx-axi-shutdown-manag
40
41 reg:
42 maxItems: 1
43
44 clocks:
45 maxItems: 1
46
47 clock-names:
48 items:
49 - const: aclk
50
51 required:
52 - compatible
53 - reg
54 - clocks
55 - clock-names
56
57 unevaluatedProperties: false
58
59 examples:
60 - |
61 fpga-bridge@100000450 {
62 compatible = "xlnx,pr-decoupler-1.00", "
63 reg = <0x10000045 0x10>;
64 clocks = <&clkc 15>;
65 clock-names = "aclk";
66 };
67 ...
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