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Linux/Documentation/devicetree/bindings/fpga/xlnx,pr-decoupler.yaml

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Diff markup

Differences between /Documentation/devicetree/bindings/fpga/xlnx,pr-decoupler.yaml (Version linux-6.12-rc7) and /Documentation/devicetree/bindings/fpga/xlnx,pr-decoupler.yaml (Version linux-6.5.13)


  1 # SPDX-License-Identifier: (GPL-2.0-only OR BS      1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2 %YAML 1.2                                           2 %YAML 1.2
  3 ---                                                 3 ---
  4 $id: http://devicetree.org/schemas/fpga/xlnx,p      4 $id: http://devicetree.org/schemas/fpga/xlnx,pr-decoupler.yaml#
  5 $schema: http://devicetree.org/meta-schemas/co      5 $schema: http://devicetree.org/meta-schemas/core.yaml#
  6                                                     6 
  7 title: Xilinx LogiCORE Partial Reconfig Decoup      7 title: Xilinx LogiCORE Partial Reconfig Decoupler/AXI shutdown manager Softcore
  8                                                     8 
  9 maintainers:                                        9 maintainers:
 10   - Nava kishore Manne <nava.kishore.manne@amd.     10   - Nava kishore Manne <nava.kishore.manne@amd.com>
 11                                                    11 
 12 allOf:                                         << 
 13   - $ref: fpga-bridge.yaml#                    << 
 14                                                << 
 15 description: |                                     12 description: |
 16   The Xilinx LogiCORE Partial Reconfig(PR) Dec     13   The Xilinx LogiCORE Partial Reconfig(PR) Decoupler manages one or more
 17   decouplers/fpga bridges. The controller can      14   decouplers/fpga bridges. The controller can decouple/disable the bridges
 18   which prevents signal changes from passing t     15   which prevents signal changes from passing through the bridge. The controller
 19   can also couple / enable the bridges which a     16   can also couple / enable the bridges which allows traffic to pass through the
 20   bridge normally.                                 17   bridge normally.
 21   Xilinx LogiCORE Dynamic Function eXchange(DF     18   Xilinx LogiCORE Dynamic Function eXchange(DFX) AXI shutdown manager Softcore
 22   is compatible with the Xilinx LogiCORE pr-de     19   is compatible with the Xilinx LogiCORE pr-decoupler. The Dynamic Function
 23   eXchange AXI shutdown manager prevents AXI t     20   eXchange AXI shutdown manager prevents AXI traffic from passing through the
 24   bridge. The controller safely handles AXI4MM     21   bridge. The controller safely handles AXI4MM and AXI4-Lite interfaces on a
 25   Reconfigurable Partition when it is undergoi     22   Reconfigurable Partition when it is undergoing dynamic reconfiguration,
 26   preventing the system deadlock that can occu     23   preventing the system deadlock that can occur if AXI transactions are
 27   interrupted by DFX.                              24   interrupted by DFX.
 28   Please refer to fpga-region.txt and fpga-bri     25   Please refer to fpga-region.txt and fpga-bridge.txt in this directory for
 29   common binding part and usage.                   26   common binding part and usage.
 30                                                    27 
 31 properties:                                        28 properties:
 32   compatible:                                      29   compatible:
 33     oneOf:                                         30     oneOf:
 34       - items:                                     31       - items:
 35           - const: xlnx,pr-decoupler-1.00          32           - const: xlnx,pr-decoupler-1.00
 36           - const: xlnx,pr-decoupler               33           - const: xlnx,pr-decoupler
 37       - items:                                     34       - items:
 38           - const: xlnx,dfx-axi-shutdown-manag     35           - const: xlnx,dfx-axi-shutdown-manager-1.00
 39           - const: xlnx,dfx-axi-shutdown-manag     36           - const: xlnx,dfx-axi-shutdown-manager
 40                                                    37 
 41   reg:                                             38   reg:
 42     maxItems: 1                                    39     maxItems: 1
 43                                                    40 
 44   clocks:                                          41   clocks:
 45     maxItems: 1                                    42     maxItems: 1
 46                                                    43 
 47   clock-names:                                     44   clock-names:
 48     items:                                         45     items:
 49       - const: aclk                                46       - const: aclk
 50                                                    47 
 51 required:                                          48 required:
 52   - compatible                                     49   - compatible
 53   - reg                                            50   - reg
 54   - clocks                                         51   - clocks
 55   - clock-names                                    52   - clock-names
 56                                                    53 
 57 unevaluatedProperties: false                   !!  54 additionalProperties: false
 58                                                    55 
 59 examples:                                          56 examples:
 60   - |                                              57   - |
 61     fpga-bridge@100000450 {                        58     fpga-bridge@100000450 {
 62       compatible = "xlnx,pr-decoupler-1.00", "     59       compatible = "xlnx,pr-decoupler-1.00", "xlnx,pr-decoupler";
 63       reg = <0x10000045 0x10>;                     60       reg = <0x10000045 0x10>;
 64       clocks = <&clkc 15>;                         61       clocks = <&clkc 15>;
 65       clock-names = "aclk";                        62       clock-names = "aclk";
 66     };                                             63     };
 67 ...                                                64 ...
                                                      

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