1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-C 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,z 4 $id: http://devicetree.org/schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Xilinx Zynq Ultrascale MPSoC FPGA Manag 7 title: Xilinx Zynq Ultrascale MPSoC FPGA Manager
8 8
9 maintainers: 9 maintainers:
10 - Nava kishore Manne <nava.kishore.manne@amd. 10 - Nava kishore Manne <nava.kishore.manne@amd.com>
11 11
12 description: | 12 description: |
13 Device Tree Bindings for Zynq Ultrascale MPS 13 Device Tree Bindings for Zynq Ultrascale MPSoC FPGA Manager.
14 The ZynqMP SoC uses the PCAP (Processor Conf 14 The ZynqMP SoC uses the PCAP (Processor Configuration Port) to
15 configure the Programmable Logic (PL). The c 15 configure the Programmable Logic (PL). The configuration uses the
16 firmware interface. 16 firmware interface.
17 17
18 properties: 18 properties:
19 compatible: 19 compatible:
20 const: xlnx,zynqmp-pcap-fpga 20 const: xlnx,zynqmp-pcap-fpga
21 21
22 required: 22 required:
23 - compatible 23 - compatible
24 24
25 additionalProperties: false 25 additionalProperties: false
26 26
27 examples: 27 examples:
28 - | 28 - |
29 firmware { 29 firmware {
30 zynqmp_firmware: zynqmp-firmware { 30 zynqmp_firmware: zynqmp-firmware {
31 zynqmp_pcap: pcap { 31 zynqmp_pcap: pcap {
32 compatible = "xlnx,zynqmp-pcap-fpga" 32 compatible = "xlnx,zynqmp-pcap-fpga";
33 }; 33 };
34 }; 34 };
35 }; 35 };
36 ... 36 ...
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