1 Specifying GPIO information for devices 1 Specifying GPIO information for devices
2 ======================================= 2 =======================================
3 3
4 1) gpios property 4 1) gpios property
5 ----------------- 5 -----------------
6 6
7 GPIO properties should be named "[<name>-]gpio 7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-exist 8 of this GPIO for the device. While a non-existent <name> is considered valid
9 for compatibility reasons (resolving to the "g 9 for compatibility reasons (resolving to the "gpios" property), it is not allowed
10 for new bindings. Also, GPIO properties named 10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
11 bindings use it, but are only supported for co 11 bindings use it, but are only supported for compatibility reasons and should not
12 be used for newer bindings since it has been d 12 be used for newer bindings since it has been deprecated.
13 13
14 GPIO properties can contain one or more GPIO p 14 GPIO properties can contain one or more GPIO phandles, but only in exceptional
15 cases should they contain more than one. If yo 15 cases should they contain more than one. If your device uses several GPIOs with
16 distinct functions, reference each of them und 16 distinct functions, reference each of them under its own property, giving it a
17 meaningful name. The only case where an array 17 meaningful name. The only case where an array of GPIOs is accepted is when
18 several GPIOs serve the same function (e.g. a 18 several GPIOs serve the same function (e.g. a parallel data line).
19 19
20 The exact purpose of each gpios property must 20 The exact purpose of each gpios property must be documented in the device tree
21 binding of the device. 21 binding of the device.
22 22
23 The following example could be used to describ 23 The following example could be used to describe GPIO pins used as device enable
24 and bit-banged data signals: 24 and bit-banged data signals:
25 25
26 gpio1: gpio1 { 26 gpio1: gpio1 {
27 gpio-controller; 27 gpio-controller;
28 #gpio-cells = <2>; 28 #gpio-cells = <2>;
29 }; 29 };
30 [...] 30 [...]
31 31
32 data-gpios = <&gpio1 12 0>, 32 data-gpios = <&gpio1 12 0>,
33 <&gpio1 13 0>, 33 <&gpio1 13 0>,
34 <&gpio1 14 0>, 34 <&gpio1 14 0>,
35 <&gpio1 15 0>; 35 <&gpio1 15 0>;
36 36
37 In the above example, &gpio1 uses 2 cells to s 37 In the above example, &gpio1 uses 2 cells to specify a gpio. The first cell is
38 a local offset to the GPIO line and the second 38 a local offset to the GPIO line and the second cell represent consumer flags,
39 such as if the consumer desire the line to be 39 such as if the consumer desire the line to be active low (inverted) or open
40 drain. This is the recommended practice. 40 drain. This is the recommended practice.
41 41
42 The exact meaning of each specifier cell is co 42 The exact meaning of each specifier cell is controller specific, and must be
43 documented in the device tree binding for the 43 documented in the device tree binding for the device, but it is strongly
44 recommended to use the two-cell approach. 44 recommended to use the two-cell approach.
45 45
46 Most controllers are specifying a generic flag 46 Most controllers are specifying a generic flag bitfield in the last cell, so
47 for these, use the macros defined in 47 for these, use the macros defined in
48 include/dt-bindings/gpio/gpio.h whenever possi 48 include/dt-bindings/gpio/gpio.h whenever possible:
49 49
50 Example of a node using GPIOs: 50 Example of a node using GPIOs:
51 51
52 node { 52 node {
53 enable-gpios = <&qe_pio_e 18 G 53 enable-gpios = <&qe_pio_e 18 GPIO_ACTIVE_HIGH>;
54 }; 54 };
55 55
56 GPIO_ACTIVE_HIGH is 0, so in this example gpio 56 GPIO_ACTIVE_HIGH is 0, so in this example gpio-specifier is "18 0" and encodes
57 GPIO pin number, and GPIO flags as accepted by 57 GPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller.
58 58
59 Optional standard bitfield specifiers for the 59 Optional standard bitfield specifiers for the last cell:
60 60
61 - Bit 0: 0 means active high, 1 means active l 61 - Bit 0: 0 means active high, 1 means active low
62 - Bit 1: 0 mean push-pull wiring, see: 62 - Bit 1: 0 mean push-pull wiring, see:
63 https://en.wikipedia.org/wiki/Push- 63 https://en.wikipedia.org/wiki/Push-pull_output
64 1 means single-ended wiring, see: 64 1 means single-ended wiring, see:
65 https://en.wikipedia.org/wiki/Singl 65 https://en.wikipedia.org/wiki/Single-ended_triode
66 - Bit 2: 0 means open-source, 1 means open dra 66 - Bit 2: 0 means open-source, 1 means open drain, see:
67 https://en.wikipedia.org/wiki/Open_ 67 https://en.wikipedia.org/wiki/Open_collector
68 - Bit 3: 0 means the output should be maintain 68 - Bit 3: 0 means the output should be maintained during sleep/low-power mode
69 1 means the output state can be lost 69 1 means the output state can be lost during sleep/low-power mode
70 - Bit 4: 0 means no pull-up resistor should be 70 - Bit 4: 0 means no pull-up resistor should be enabled
71 1 means a pull-up resistor should be 71 1 means a pull-up resistor should be enabled
72 This setting only applies to hardware 72 This setting only applies to hardware with a simple on/off
73 control for pull-up configuration. If 73 control for pull-up configuration. If the hardware has more
74 elaborate pull-up configuration, it s 74 elaborate pull-up configuration, it should be represented
75 using a pin control binding. 75 using a pin control binding.
76 - Bit 5: 0 means no pull-down resistor should 76 - Bit 5: 0 means no pull-down resistor should be enabled
77 1 means a pull-down resistor should b 77 1 means a pull-down resistor should be enabled
78 This setting only applies to hardware 78 This setting only applies to hardware with a simple on/off
79 control for pull-down configuration. 79 control for pull-down configuration. If the hardware has more
80 elaborate pull-down configuration, it 80 elaborate pull-down configuration, it should be represented
81 using a pin control binding. 81 using a pin control binding.
82 82
83 1.1) GPIO specifier best practices 83 1.1) GPIO specifier best practices
84 ---------------------------------- 84 ----------------------------------
85 85
86 A gpio-specifier should contain a flag indicat 86 A gpio-specifier should contain a flag indicating the GPIO polarity; active-
87 high or active-low. If it does, the following 87 high or active-low. If it does, the following best practices should be
88 followed: 88 followed:
89 89
90 The gpio-specifier's polarity flag should repr 90 The gpio-specifier's polarity flag should represent the physical level at the
91 GPIO controller that achieves (or represents, 91 GPIO controller that achieves (or represents, for inputs) a logically asserted
92 value at the device. The exact definition of l 92 value at the device. The exact definition of logically asserted should be
93 defined by the binding for the device. If the 93 defined by the binding for the device. If the board inverts the signal between
94 the GPIO controller and the device, then the g 94 the GPIO controller and the device, then the gpio-specifier will represent the
95 opposite physical level than the signal at the 95 opposite physical level than the signal at the device's pin.
96 96
97 When the device's signal polarity is configura 97 When the device's signal polarity is configurable, the binding for the
98 device must either: 98 device must either:
99 99
100 a) Define a single static polarity for the sig 100 a) Define a single static polarity for the signal, with the expectation that
101 any software using that binding would statical 101 any software using that binding would statically program the device to use
102 that signal polarity. 102 that signal polarity.
103 103
104 The static choice of polarity may be either: 104 The static choice of polarity may be either:
105 105
106 a1) (Preferred) Dictated by a binding-specific 106 a1) (Preferred) Dictated by a binding-specific DT property.
107 107
108 or: 108 or:
109 109
110 a2) Defined statically by the DT binding itsel 110 a2) Defined statically by the DT binding itself.
111 111
112 In particular, the polarity cannot be derived 112 In particular, the polarity cannot be derived from the gpio-specifier, since
113 that would prevent the DT from separately repr 113 that would prevent the DT from separately representing the two orthogonal
114 concepts of configurable signal polarity in th 114 concepts of configurable signal polarity in the device, and possible board-
115 level signal inversion. 115 level signal inversion.
116 116
117 or: 117 or:
118 118
119 b) Pick a single option for device signal pola 119 b) Pick a single option for device signal polarity, and document this choice
120 in the binding. The gpio-specifier should repr 120 in the binding. The gpio-specifier should represent the polarity of the signal
121 (at the GPIO controller) assuming that the dev 121 (at the GPIO controller) assuming that the device is configured for this
122 particular signal polarity choice. If software 122 particular signal polarity choice. If software chooses to program the device
123 to generate or receive a signal of the opposit 123 to generate or receive a signal of the opposite polarity, software will be
124 responsible for correctly interpreting (invert 124 responsible for correctly interpreting (inverting) the GPIO signal at the GPIO
125 controller. 125 controller.
126 126
127 2) gpio-controller nodes 127 2) gpio-controller nodes
128 ------------------------ 128 ------------------------
129 129
130 Every GPIO controller node must contain both a 130 Every GPIO controller node must contain both an empty "gpio-controller"
131 property, and a #gpio-cells integer property, 131 property, and a #gpio-cells integer property, which indicates the number of
132 cells in a gpio-specifier. 132 cells in a gpio-specifier.
133 133
134 Some system-on-chips (SoCs) use the concept of 134 Some system-on-chips (SoCs) use the concept of GPIO banks. A GPIO bank is an
135 instance of a hardware IP core on a silicon di 135 instance of a hardware IP core on a silicon die, usually exposed to the
136 programmer as a coherent range of I/O addresse 136 programmer as a coherent range of I/O addresses. Usually each such bank is
137 exposed in the device tree as an individual gp 137 exposed in the device tree as an individual gpio-controller node, reflecting
138 the fact that the hardware was synthesized by 138 the fact that the hardware was synthesized by reusing the same IP block a
139 few times over. 139 few times over.
140 140
141 Optionally, a GPIO controller may have a "ngpi 141 Optionally, a GPIO controller may have a "ngpios" property. This property
142 indicates the number of in-use slots of availa 142 indicates the number of in-use slots of available slots for GPIOs. The
143 typical example is something like this: the ha 143 typical example is something like this: the hardware register is 32 bits
144 wide, but only 18 of the bits have a physical 144 wide, but only 18 of the bits have a physical counterpart. The driver is
145 generally written so that all 32 bits can be u 145 generally written so that all 32 bits can be used, but the IP block is reused
146 in a lot of designs, some using all 32 bits, s 146 in a lot of designs, some using all 32 bits, some using 18 and some using
147 12. In this case, setting "ngpios = <18>;" inf 147 12. In this case, setting "ngpios = <18>;" informs the driver that only the
148 first 18 GPIOs, at local offset 0 .. 17, are i 148 first 18 GPIOs, at local offset 0 .. 17, are in use.
149 149
150 If these GPIOs do not happen to be the first N 150 If these GPIOs do not happen to be the first N GPIOs at offset 0...N-1, an
151 additional set of tuples is needed to specify 151 additional set of tuples is needed to specify which GPIOs are unusable, with
152 the gpio-reserved-ranges binding. This propert 152 the gpio-reserved-ranges binding. This property indicates the start and size
153 of the GPIOs that can't be used. 153 of the GPIOs that can't be used.
154 154
155 Optionally, a GPIO controller may have a "gpio 155 Optionally, a GPIO controller may have a "gpio-line-names" property. This is
156 an array of strings defining the names of the 156 an array of strings defining the names of the GPIO lines going out of the
157 GPIO controller. 157 GPIO controller.
158 158
159 For lines which are routed to on-board devices 159 For lines which are routed to on-board devices, this name should be
160 the most meaningful producer name for the syst 160 the most meaningful producer name for the system, such as a rail name
161 indicating the usage. Package names, such as a 161 indicating the usage. Package names, such as a pin name, are discouraged:
162 such lines have opaque names (since they are b 162 such lines have opaque names (since they are by definition general-purpose)
163 and such names are usually not very helpful. F 163 and such names are usually not very helpful. For example "MMC-CD", "Red LED
164 Vdd" and "ethernet reset" are reasonable line 164 Vdd" and "ethernet reset" are reasonable line names as they describe what
165 the line is used for. "GPIO0" is not a good na 165 the line is used for. "GPIO0" is not a good name to give to a GPIO line
166 that is hard-wired to a specific device. 166 that is hard-wired to a specific device.
167 167
168 However, in the case of lines that are routed 168 However, in the case of lines that are routed to a general purpose header
169 (e.g. the Raspberry Pi 40-pin header), and the 169 (e.g. the Raspberry Pi 40-pin header), and therefore are not hard-wired to
170 specific devices, using a pin number or the na 170 specific devices, using a pin number or the names on the header is fine
171 provided these are real (preferably unique) na 171 provided these are real (preferably unique) names. Using an SoC's pad name
172 or package name, or names made up from kernel- 172 or package name, or names made up from kernel-internal software constructs,
173 are strongly discouraged. For example "pin8 [g 173 are strongly discouraged. For example "pin8 [gpio14/uart0_txd]" is fine
174 if the board's documentation labels pin 8 as s 174 if the board's documentation labels pin 8 as such. However "PortB_24" (an
175 example of a name from an SoC's reference manu 175 example of a name from an SoC's reference manual) would not be desirable.
176 176
177 In either case placeholders are discouraged: r 177 In either case placeholders are discouraged: rather use the "" (blank
178 string) if the use of the GPIO line is undefin 178 string) if the use of the GPIO line is undefined in your design. Ideally,
179 try to add comments to the dts file describing 179 try to add comments to the dts file describing the naming the convention
180 you have chosen, and specifying from where the 180 you have chosen, and specifying from where the names are derived.
181 181
182 The names are assigned starting from line offs 182 The names are assigned starting from line offset 0, from left to right,
183 from the passed array. An incomplete array (wh 183 from the passed array. An incomplete array (where the number of passed
184 names is less than ngpios) will be used up unt 184 names is less than ngpios) will be used up until the last provided valid
185 line index. 185 line index.
186 186
187 Example: 187 Example:
188 188
189 gpio-controller@00000000 { 189 gpio-controller@00000000 {
190 compatible = "foo"; 190 compatible = "foo";
191 reg = <0x00000000 0x1000>; 191 reg = <0x00000000 0x1000>;
192 gpio-controller; 192 gpio-controller;
193 #gpio-cells = <2>; 193 #gpio-cells = <2>;
194 ngpios = <18>; 194 ngpios = <18>;
195 gpio-reserved-ranges = <0 4>, <12 2>; 195 gpio-reserved-ranges = <0 4>, <12 2>;
196 gpio-line-names = "MMC-CD", "MMC-WP", 196 gpio-line-names = "MMC-CD", "MMC-WP", "VDD eth", "RST eth", "LED R",
197 "LED G", "LED B", "Col A", "Co 197 "LED G", "LED B", "Col A", "Col B", "Col C", "Col D",
198 "Row A", "Row B", "Row C", "Ro 198 "Row A", "Row B", "Row C", "Row D", "NMI button",
199 "poweroff", "reset"; 199 "poweroff", "reset";
200 } 200 }
201 201
202 The GPIO chip may contain GPIO hog definitions 202 The GPIO chip may contain GPIO hog definitions. GPIO hogging is a mechanism
203 providing automatic GPIO request and configura 203 providing automatic GPIO request and configuration as part of the
204 gpio-controller's driver probe function. 204 gpio-controller's driver probe function.
205 205
206 Each GPIO hog definition is represented as a c 206 Each GPIO hog definition is represented as a child node of the GPIO controller.
207 Required properties: 207 Required properties:
208 - gpio-hog: A property specifying that this 208 - gpio-hog: A property specifying that this child node represents a GPIO hog.
209 - gpios: Store the GPIO information (id, 209 - gpios: Store the GPIO information (id, flags, ...) for each GPIO to
210 affect. Shall contain an integer 210 affect. Shall contain an integer multiple of the number of cells
211 specified in its parent node (GP 211 specified in its parent node (GPIO controller node).
212 Only one of the following properties scanned i 212 Only one of the following properties scanned in the order shown below.
213 This means that when multiple properties are p 213 This means that when multiple properties are present they will be searched
214 in the order presented below and the first mat 214 in the order presented below and the first match is taken as the intended
215 configuration. 215 configuration.
216 - input: A property specifying to set the 216 - input: A property specifying to set the GPIO direction as input.
217 - output-low A property specifying to set the 217 - output-low A property specifying to set the GPIO direction as output with
218 the value low. 218 the value low.
219 - output-high A property specifying to set the 219 - output-high A property specifying to set the GPIO direction as output with
220 the value high. 220 the value high.
221 221
222 Optional properties: 222 Optional properties:
223 - line-name: The GPIO label name. If not pres 223 - line-name: The GPIO label name. If not present the node name is used.
224 224
225 Example of two SOC GPIO banks defined as gpio- 225 Example of two SOC GPIO banks defined as gpio-controller nodes:
226 226
227 qe_pio_a: gpio-controller@1400 { 227 qe_pio_a: gpio-controller@1400 {
228 compatible = "fsl,qe-pario-ban 228 compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank";
229 reg = <0x1400 0x18>; 229 reg = <0x1400 0x18>;
230 gpio-controller; 230 gpio-controller;
231 #gpio-cells = <2>; 231 #gpio-cells = <2>;
232 232
233 line_b-hog { 233 line_b-hog {
234 gpio-hog; 234 gpio-hog;
235 gpios = <6 0>; 235 gpios = <6 0>;
236 output-low; 236 output-low;
237 line-name = "foo-bar-g 237 line-name = "foo-bar-gpio";
238 }; 238 };
239 }; 239 };
240 240
241 qe_pio_e: gpio-controller@1460 { 241 qe_pio_e: gpio-controller@1460 {
242 compatible = "fsl,qe-pario-ban 242 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
243 reg = <0x1460 0x18>; 243 reg = <0x1460 0x18>;
244 gpio-controller; 244 gpio-controller;
245 #gpio-cells = <2>; 245 #gpio-cells = <2>;
246 }; 246 };
247 247
248 2.1) gpio- and pin-controller interaction 248 2.1) gpio- and pin-controller interaction
249 ----------------------------------------- 249 -----------------------------------------
250 250
251 Some or all of the GPIOs provided by a GPIO co 251 Some or all of the GPIOs provided by a GPIO controller may be routed to pins
252 on the package via a pin controller. This allo 252 on the package via a pin controller. This allows muxing those pins between
253 GPIO and other functions. It is a fairly commo 253 GPIO and other functions. It is a fairly common practice among silicon
254 engineers. 254 engineers.
255 255
256 2.2) Ordinary (numerical) GPIO ranges 256 2.2) Ordinary (numerical) GPIO ranges
257 ------------------------------------- 257 -------------------------------------
258 258
259 It is useful to represent which GPIOs correspo 259 It is useful to represent which GPIOs correspond to which pins on which pin
260 controllers. The gpio-ranges property describe 260 controllers. The gpio-ranges property described below represents this with
261 a discrete set of ranges mapping pins from the 261 a discrete set of ranges mapping pins from the pin controller local number space
262 to pins in the GPIO controller local number sp 262 to pins in the GPIO controller local number space.
263 263
264 The format is: <[pin controller phandle], [GPI 264 The format is: <[pin controller phandle], [GPIO controller offset],
265 [pin controller offset], [numb 265 [pin controller offset], [number of pins]>;
266 266
267 The GPIO controller offset pertains to the GPI 267 The GPIO controller offset pertains to the GPIO controller node containing the
268 range definition. 268 range definition.
269 269
270 The pin controller node referenced by the phan 270 The pin controller node referenced by the phandle must conform to the bindings
271 described in pinctrl/pinctrl-bindings.txt. 271 described in pinctrl/pinctrl-bindings.txt.
272 272
273 Each offset runs from 0 to N. It is perfectly 273 Each offset runs from 0 to N. It is perfectly fine to pile any number of
274 ranges with just one pin-to-GPIO line mapping 274 ranges with just one pin-to-GPIO line mapping if the ranges are concocted, but
275 in practice these ranges are often lumped in d 275 in practice these ranges are often lumped in discrete sets.
276 276
277 Example: 277 Example:
278 278
279 gpio-ranges = <&foo 0 20 10>, <&bar 10 50 279 gpio-ranges = <&foo 0 20 10>, <&bar 10 50 20>;
280 280
281 This means: 281 This means:
282 - pins 20..29 on pin controller "foo" is mappe 282 - pins 20..29 on pin controller "foo" is mapped to GPIO line 0..9 and
283 - pins 50..69 on pin controller "bar" is mappe 283 - pins 50..69 on pin controller "bar" is mapped to GPIO line 10..29
284 284
285 285
286 Verbose example: 286 Verbose example:
287 287
288 qe_pio_e: gpio-controller@1460 { 288 qe_pio_e: gpio-controller@1460 {
289 #gpio-cells = <2>; 289 #gpio-cells = <2>;
290 compatible = "fsl,qe-pario-ban 290 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
291 reg = <0x1460 0x18>; 291 reg = <0x1460 0x18>;
292 gpio-controller; 292 gpio-controller;
293 gpio-ranges = <&pinctrl1 0 20 293 gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>;
294 }; 294 };
295 295
296 Here, a single GPIO controller has GPIOs 0..9 296 Here, a single GPIO controller has GPIOs 0..9 routed to pin controller
297 pinctrl1's pins 20..29, and GPIOs 10..29 route 297 pinctrl1's pins 20..29, and GPIOs 10..29 routed to pin controller pinctrl2's
298 pins 50..69. 298 pins 50..69.
299 299
300 300
301 2.3) GPIO ranges from named pin groups 301 2.3) GPIO ranges from named pin groups
302 -------------------------------------- 302 --------------------------------------
303 303
304 It is also possible to use pin groups for gpio 304 It is also possible to use pin groups for gpio ranges when pin groups are the
305 easiest and most convenient mapping. 305 easiest and most convenient mapping.
306 306
307 Both both <pinctrl-base> and <count> must set 307 Both both <pinctrl-base> and <count> must set to 0 when using named pin groups
308 names. 308 names.
309 309
310 The property gpio-ranges-group-names must cont 310 The property gpio-ranges-group-names must contain exactly one string for each
311 range. 311 range.
312 312
313 Elements of gpio-ranges-group-names must conta 313 Elements of gpio-ranges-group-names must contain the name of a pin group
314 defined in the respective pin controller. The 314 defined in the respective pin controller. The number of pins/GPIO lines in the
315 range is the number of pins in that pin group. 315 range is the number of pins in that pin group. The number of pins of that
316 group is defined int the implementation and no 316 group is defined int the implementation and not in the device tree.
317 317
318 If numerical and named pin groups are mixed, t 318 If numerical and named pin groups are mixed, the string corresponding to a
319 numerical pin range in gpio-ranges-group-names 319 numerical pin range in gpio-ranges-group-names must be empty.
320 320
321 Example: 321 Example:
322 322
323 gpio_pio_i: gpio-controller@14b0 { 323 gpio_pio_i: gpio-controller@14b0 {
324 #gpio-cells = <2>; 324 #gpio-cells = <2>;
325 compatible = "fsl,qe-pario-ban 325 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
326 reg = <0x1480 0x18>; 326 reg = <0x1480 0x18>;
327 gpio-controller; 327 gpio-controller;
328 gpio-ranges = 328 gpio-ranges = <&pinctrl1 0 20 10>,
329 329 <&pinctrl2 10 0 0>,
330 330 <&pinctrl1 15 0 10>,
331 331 <&pinctrl2 25 0 0>;
332 gpio-ranges-group-names = 332 gpio-ranges-group-names = "",
333 333 "foo",
334 334 "",
335 335 "bar";
336 }; 336 };
337 337
338 Here, three GPIO ranges are defined referring 338 Here, three GPIO ranges are defined referring to two pin controllers.
339 339
340 pinctrl1 GPIO ranges are defined using pin num 340 pinctrl1 GPIO ranges are defined using pin numbers whereas the GPIO ranges
341 in pinctrl2 are defined using the pin groups n 341 in pinctrl2 are defined using the pin groups named "foo" and "bar".
342 342
343 Previous versions of this binding required all 343 Previous versions of this binding required all pin controller nodes that
344 were referenced by any gpio-ranges property to 344 were referenced by any gpio-ranges property to contain a property named
345 #gpio-range-cells with value <3>. This require 345 #gpio-range-cells with value <3>. This requirement is now deprecated.
346 However, that property may still exist in olde 346 However, that property may still exist in older device trees for
347 compatibility reasons, and would still be requ 347 compatibility reasons, and would still be required even in new device
348 trees that need to be compatible with older so 348 trees that need to be compatible with older software.
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