1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-C 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/ 4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvjpg.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: NVIDIA Tegra NVJPG 7 title: NVIDIA Tegra NVJPG
8 8
9 description: | 9 description: |
10 NVJPG is the hardware JPEG decoder and encod 10 NVJPG is the hardware JPEG decoder and encoder present on NVIDIA Tegra210
11 and newer chips. It is located on the Host1x 11 and newer chips. It is located on the Host1x bus and typically programmed
12 through Host1x channels. 12 through Host1x channels.
13 13
14 maintainers: 14 maintainers:
15 - Thierry Reding <treding@gmail.com> 15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com> 16 - Mikko Perttunen <mperttunen@nvidia.com>
17 17
18 properties: 18 properties:
19 $nodename: 19 $nodename:
20 pattern: "^nvjpg@[0-9a-f]*$" 20 pattern: "^nvjpg@[0-9a-f]*$"
21 21
22 compatible: 22 compatible:
23 enum: 23 enum:
24 - nvidia,tegra210-nvjpg 24 - nvidia,tegra210-nvjpg
25 - nvidia,tegra186-nvjpg 25 - nvidia,tegra186-nvjpg
26 - nvidia,tegra194-nvjpg 26 - nvidia,tegra194-nvjpg
27 27
28 reg: 28 reg:
29 maxItems: 1 29 maxItems: 1
30 30
31 clocks: 31 clocks:
32 maxItems: 1 32 maxItems: 1
33 33
34 clock-names: 34 clock-names:
35 items: 35 items:
36 - const: nvjpg 36 - const: nvjpg
37 37
38 resets: 38 resets:
39 maxItems: 1 39 maxItems: 1
40 40
41 reset-names: 41 reset-names:
42 items: 42 items:
43 - const: nvjpg 43 - const: nvjpg
44 44
45 power-domains: 45 power-domains:
46 maxItems: 1 46 maxItems: 1
47 47
48 iommus: 48 iommus:
49 maxItems: 1 49 maxItems: 1
50 50
51 dma-coherent: true 51 dma-coherent: true
52 52
53 interconnects: 53 interconnects:
54 items: 54 items:
55 - description: DMA read memory client 55 - description: DMA read memory client
56 - description: DMA write memory client 56 - description: DMA write memory client
57 57
58 interconnect-names: 58 interconnect-names:
59 items: 59 items:
60 - const: dma-mem 60 - const: dma-mem
61 - const: write 61 - const: write
62 62
63 required: 63 required:
64 - compatible 64 - compatible
65 - reg 65 - reg
66 - clocks 66 - clocks
67 - clock-names 67 - clock-names
68 - resets 68 - resets
69 - reset-names 69 - reset-names
70 - power-domains 70 - power-domains
71 71
72 additionalProperties: false 72 additionalProperties: false
73 73
74 examples: 74 examples:
75 - | 75 - |
76 #include <dt-bindings/clock/tegra186-clock 76 #include <dt-bindings/clock/tegra186-clock.h>
77 #include <dt-bindings/memory/tegra186-mc.h 77 #include <dt-bindings/memory/tegra186-mc.h>
78 #include <dt-bindings/power/tegra186-power 78 #include <dt-bindings/power/tegra186-powergate.h>
79 #include <dt-bindings/reset/tegra186-reset 79 #include <dt-bindings/reset/tegra186-reset.h>
80 80
81 nvjpg@15380000 { 81 nvjpg@15380000 {
82 compatible = "nvidia,tegra186-nvjp 82 compatible = "nvidia,tegra186-nvjpg";
83 reg = <0x15380000 0x40000>; 83 reg = <0x15380000 0x40000>;
84 clocks = <&bpmp TEGRA186_CLK_NVJPG 84 clocks = <&bpmp TEGRA186_CLK_NVJPG>;
85 clock-names = "nvjpg"; 85 clock-names = "nvjpg";
86 resets = <&bpmp TEGRA186_RESET_NVJ 86 resets = <&bpmp TEGRA186_RESET_NVJPG>;
87 reset-names = "nvjpg"; 87 reset-names = "nvjpg";
88 88
89 power-domains = <&bpmp TEGRA186_PO 89 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>;
90 interconnects = <&mc TEGRA186_MEMO 90 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>,
91 <&mc TEGRA186_MEMO 91 <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>;
92 interconnect-names = "dma-mem", "w 92 interconnect-names = "dma-mem", "write";
93 iommus = <&smmu TEGRA186_SID_NVJPG 93 iommus = <&smmu TEGRA186_SID_NVJPG>;
94 }; 94 };
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