1 NVIDIA Tegra Graphics Processing Units
2
3 Required properties:
4 - compatible: "nvidia,<gpu>"
5 Currently recognized values:
6 - nvidia,gk20a
7 - nvidia,gm20b
8 - nvidia,gp10b
9 - nvidia,gv11b
10 - reg: Physical base address and length of the
11 Must contain two entries:
12 - first entry for bar0
13 - second entry for bar1
14 - interrupts: Must contain an entry for each e
15 See ../interrupt-controller/interrupts.txt f
16 - interrupt-names: Must include the following
17 - stall
18 - nonstall
19 - vdd-supply: regulator for supply voltage. On
20 power domains.
21 - clocks: Must contain an entry for each entry
22 See ../clocks/clock-bindings.txt for details
23 - clock-names: Must include the following entr
24 - gpu
25 - pwr
26 If the compatible string is "nvidia,gm20b", th
27 is also required:
28 - ref
29 If the compatible string is "nvidia,gv11b", th
30 required:
31 - fuse
32 - resets: Must contain an entry for each entry
33 See ../reset/reset.txt for details.
34 - reset-names: Must include the following entr
35 - gpu
36 - power-domains: GPUs that make use of power d
37 instead of vdd-supply. Currently "nvidia,gp1
38
39 Optional properties:
40 - iommus: A reference to the IOMMU. See ../iom
41
42 Example for GK20A:
43
44 gpu@57000000 {
45 compatible = "nvidia,gk20a";
46 reg = <0x0 0x57000000 0x0 0x01
47 <0x0 0x58000000 0x0 0x01
48 interrupts = <GIC_SPI 157 IRQ_
49 <GIC_SPI 158 IRQ_
50 interrupt-names = "stall", "no
51 vdd-supply = <&vdd_gpu>;
52 clocks = <&tegra_car TEGRA124_
53 <&tegra_car TEGRA124_
54 clock-names = "gpu", "pwr";
55 resets = <&tegra_car 184>;
56 reset-names = "gpu";
57 iommus = <&mc TEGRA_SWGROUP_GP
58 };
59
60 Example for GM20B:
61
62 gpu@57000000 {
63 compatible = "nvidia,gm20b";
64 reg = <0x0 0x57000000 0x0 0x01
65 <0x0 0x58000000 0x0 0x01
66 interrupts = <GIC_SPI 157 IRQ_
67 <GIC_SPI 158 IRQ_
68 interrupt-names = "stall", "no
69 clocks = <&tegra_car TEGRA210_
70 <&tegra_car TEGRA210_
71 <&tegra_car TEGRA210_
72 clock-names = "gpu", "pwr", "r
73 resets = <&tegra_car 184>;
74 reset-names = "gpu";
75 iommus = <&mc TEGRA_SWGROUP_GP
76 };
77
78 Example for GP10B:
79
80 gpu@17000000 {
81 compatible = "nvidia,gp10b";
82 reg = <0x0 0x17000000 0x0 0x10
83 <0x0 0x18000000 0x0 0x10
84 interrupts = <GIC_SPI 70 IRQ_T
85 GIC_SPI 71 IRQ_T
86 interrupt-names = "stall", "no
87 clocks = <&bpmp TEGRA186_CLK_G
88 <&bpmp TEGRA186_CLK_G
89 clock-names = "gpu", "pwr";
90 resets = <&bpmp TEGRA186_RESET
91 reset-names = "gpu";
92 power-domains = <&bpmp TEGRA18
93 iommus = <&smmu TEGRA186_SID_G
94 };
95
96 Example for GV11B:
97
98 gpu@17000000 {
99 compatible = "nvidia,gv11b";
100 reg = <0x17000000 0x1000000>,
101 <0x18000000 0x1000000>;
102 interrupts = <GIC_SPI 70 IRQ_T
103 <GIC_SPI 71 IRQ_T
104 interrupt-names = "stall", "no
105 clocks = <&bpmp TEGRA194_CLK_G
106 <&bpmp TEGRA194_CLK_G
107 <&bpmp TEGRA194_CLK_F
108 clock-names = "gpu", "pwr", "f
109 resets = <&bpmp TEGRA194_RESET
110 reset-names = "gpu";
111 dma-coherent;
112
113 power-domains = <&bpmp TEGRA19
114 iommus = <&smmu TEGRA194_SID_G
115 };
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