1 NVIDIA Tegra Graphics Processing Units 1 NVIDIA Tegra Graphics Processing Units
2 2
3 Required properties: 3 Required properties:
4 - compatible: "nvidia,<gpu>" 4 - compatible: "nvidia,<gpu>"
5 Currently recognized values: 5 Currently recognized values:
6 - nvidia,gk20a 6 - nvidia,gk20a
7 - nvidia,gm20b 7 - nvidia,gm20b
8 - nvidia,gp10b <<
9 - nvidia,gv11b <<
10 - reg: Physical base address and length of the 8 - reg: Physical base address and length of the controller's registers.
11 Must contain two entries: 9 Must contain two entries:
12 - first entry for bar0 10 - first entry for bar0
13 - second entry for bar1 11 - second entry for bar1
14 - interrupts: Must contain an entry for each e 12 - interrupts: Must contain an entry for each entry in interrupt-names.
15 See ../interrupt-controller/interrupts.txt f 13 See ../interrupt-controller/interrupts.txt for details.
16 - interrupt-names: Must include the following 14 - interrupt-names: Must include the following entries:
17 - stall 15 - stall
18 - nonstall 16 - nonstall
19 - vdd-supply: regulator for supply voltage. On !! 17 - vdd-supply: regulator for supply voltage.
20 power domains. <<
21 - clocks: Must contain an entry for each entry 18 - clocks: Must contain an entry for each entry in clock-names.
22 See ../clocks/clock-bindings.txt for details 19 See ../clocks/clock-bindings.txt for details.
23 - clock-names: Must include the following entr 20 - clock-names: Must include the following entries:
24 - gpu 21 - gpu
25 - pwr 22 - pwr
26 If the compatible string is "nvidia,gm20b", th 23 If the compatible string is "nvidia,gm20b", then the following clock
27 is also required: 24 is also required:
28 - ref 25 - ref
29 If the compatible string is "nvidia,gv11b", th <<
30 required: <<
31 - fuse <<
32 - resets: Must contain an entry for each entry 26 - resets: Must contain an entry for each entry in reset-names.
33 See ../reset/reset.txt for details. 27 See ../reset/reset.txt for details.
34 - reset-names: Must include the following entr 28 - reset-names: Must include the following entries:
35 - gpu 29 - gpu
36 - power-domains: GPUs that make use of power d <<
37 instead of vdd-supply. Currently "nvidia,gp1 <<
38 30
39 Optional properties: 31 Optional properties:
40 - iommus: A reference to the IOMMU. See ../iom 32 - iommus: A reference to the IOMMU. See ../iommu/iommu.txt for details.
41 33
42 Example for GK20A: 34 Example for GK20A:
43 35
44 gpu@57000000 { 36 gpu@57000000 {
45 compatible = "nvidia,gk20a"; 37 compatible = "nvidia,gk20a";
46 reg = <0x0 0x57000000 0x0 0x01 38 reg = <0x0 0x57000000 0x0 0x01000000>,
47 <0x0 0x58000000 0x0 0x01 39 <0x0 0x58000000 0x0 0x01000000>;
48 interrupts = <GIC_SPI 157 IRQ_ 40 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
49 <GIC_SPI 158 IRQ_ 41 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
50 interrupt-names = "stall", "no 42 interrupt-names = "stall", "nonstall";
51 vdd-supply = <&vdd_gpu>; 43 vdd-supply = <&vdd_gpu>;
52 clocks = <&tegra_car TEGRA124_ 44 clocks = <&tegra_car TEGRA124_CLK_GPU>,
53 <&tegra_car TEGRA124_ 45 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
54 clock-names = "gpu", "pwr"; 46 clock-names = "gpu", "pwr";
55 resets = <&tegra_car 184>; 47 resets = <&tegra_car 184>;
56 reset-names = "gpu"; 48 reset-names = "gpu";
57 iommus = <&mc TEGRA_SWGROUP_GP 49 iommus = <&mc TEGRA_SWGROUP_GPU>;
>> 50 status = "disabled";
58 }; 51 };
59 52
60 Example for GM20B: 53 Example for GM20B:
61 54
62 gpu@57000000 { 55 gpu@57000000 {
63 compatible = "nvidia,gm20b"; 56 compatible = "nvidia,gm20b";
64 reg = <0x0 0x57000000 0x0 0x01 57 reg = <0x0 0x57000000 0x0 0x01000000>,
65 <0x0 0x58000000 0x0 0x01 58 <0x0 0x58000000 0x0 0x01000000>;
66 interrupts = <GIC_SPI 157 IRQ_ 59 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_SPI 158 IRQ_ 60 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
68 interrupt-names = "stall", "no 61 interrupt-names = "stall", "nonstall";
69 clocks = <&tegra_car TEGRA210_ 62 clocks = <&tegra_car TEGRA210_CLK_GPU>,
70 <&tegra_car TEGRA210_ 63 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
71 <&tegra_car TEGRA210_ 64 <&tegra_car TEGRA210_CLK_PLL_G_REF>;
72 clock-names = "gpu", "pwr", "r 65 clock-names = "gpu", "pwr", "ref";
73 resets = <&tegra_car 184>; 66 resets = <&tegra_car 184>;
74 reset-names = "gpu"; 67 reset-names = "gpu";
75 iommus = <&mc TEGRA_SWGROUP_GP 68 iommus = <&mc TEGRA_SWGROUP_GPU>;
76 }; !! 69 status = "disabled";
77 <<
78 Example for GP10B: <<
79 <<
80 gpu@17000000 { <<
81 compatible = "nvidia,gp10b"; <<
82 reg = <0x0 0x17000000 0x0 0x10 <<
83 <0x0 0x18000000 0x0 0x10 <<
84 interrupts = <GIC_SPI 70 IRQ_T <<
85 GIC_SPI 71 IRQ_T <<
86 interrupt-names = "stall", "no <<
87 clocks = <&bpmp TEGRA186_CLK_G <<
88 <&bpmp TEGRA186_CLK_G <<
89 clock-names = "gpu", "pwr"; <<
90 resets = <&bpmp TEGRA186_RESET <<
91 reset-names = "gpu"; <<
92 power-domains = <&bpmp TEGRA18 <<
93 iommus = <&smmu TEGRA186_SID_G <<
94 }; <<
95 <<
96 Example for GV11B: <<
97 <<
98 gpu@17000000 { <<
99 compatible = "nvidia,gv11b"; <<
100 reg = <0x17000000 0x1000000>, <<
101 <0x18000000 0x1000000>; <<
102 interrupts = <GIC_SPI 70 IRQ_T <<
103 <GIC_SPI 71 IRQ_T <<
104 interrupt-names = "stall", "no <<
105 clocks = <&bpmp TEGRA194_CLK_G <<
106 <&bpmp TEGRA194_CLK_G <<
107 <&bpmp TEGRA194_CLK_F <<
108 clock-names = "gpu", "pwr", "f <<
109 resets = <&bpmp TEGRA194_RESET <<
110 reset-names = "gpu"; <<
111 dma-coherent; <<
112 <<
113 power-domains = <&bpmp TEGRA19 <<
114 iommus = <&smmu TEGRA194_SID_G <<
115 }; 70 };
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