1 NVIDIA Tegra Graphics Processing Units 1 NVIDIA Tegra Graphics Processing Units
2 2
3 Required properties: 3 Required properties:
4 - compatible: "nvidia,<gpu>" 4 - compatible: "nvidia,<gpu>"
5 Currently recognized values: 5 Currently recognized values:
6 - nvidia,gk20a 6 - nvidia,gk20a
7 - nvidia,gm20b 7 - nvidia,gm20b
8 - nvidia,gp10b 8 - nvidia,gp10b
9 - nvidia,gv11b <<
10 - reg: Physical base address and length of the 9 - reg: Physical base address and length of the controller's registers.
11 Must contain two entries: 10 Must contain two entries:
12 - first entry for bar0 11 - first entry for bar0
13 - second entry for bar1 12 - second entry for bar1
14 - interrupts: Must contain an entry for each e 13 - interrupts: Must contain an entry for each entry in interrupt-names.
15 See ../interrupt-controller/interrupts.txt f 14 See ../interrupt-controller/interrupts.txt for details.
16 - interrupt-names: Must include the following 15 - interrupt-names: Must include the following entries:
17 - stall 16 - stall
18 - nonstall 17 - nonstall
19 - vdd-supply: regulator for supply voltage. On 18 - vdd-supply: regulator for supply voltage. Only required for GPUs not using
20 power domains. 19 power domains.
21 - clocks: Must contain an entry for each entry 20 - clocks: Must contain an entry for each entry in clock-names.
22 See ../clocks/clock-bindings.txt for details 21 See ../clocks/clock-bindings.txt for details.
23 - clock-names: Must include the following entr 22 - clock-names: Must include the following entries:
24 - gpu 23 - gpu
25 - pwr 24 - pwr
26 If the compatible string is "nvidia,gm20b", th 25 If the compatible string is "nvidia,gm20b", then the following clock
27 is also required: 26 is also required:
28 - ref 27 - ref
29 If the compatible string is "nvidia,gv11b", th <<
30 required: <<
31 - fuse <<
32 - resets: Must contain an entry for each entry 28 - resets: Must contain an entry for each entry in reset-names.
33 See ../reset/reset.txt for details. 29 See ../reset/reset.txt for details.
34 - reset-names: Must include the following entr 30 - reset-names: Must include the following entries:
35 - gpu 31 - gpu
36 - power-domains: GPUs that make use of power d 32 - power-domains: GPUs that make use of power domains can define this property
37 instead of vdd-supply. Currently "nvidia,gp1 33 instead of vdd-supply. Currently "nvidia,gp10b" makes use of this.
38 34
39 Optional properties: 35 Optional properties:
40 - iommus: A reference to the IOMMU. See ../iom 36 - iommus: A reference to the IOMMU. See ../iommu/iommu.txt for details.
41 37
42 Example for GK20A: 38 Example for GK20A:
43 39
44 gpu@57000000 { 40 gpu@57000000 {
45 compatible = "nvidia,gk20a"; 41 compatible = "nvidia,gk20a";
46 reg = <0x0 0x57000000 0x0 0x01 42 reg = <0x0 0x57000000 0x0 0x01000000>,
47 <0x0 0x58000000 0x0 0x01 43 <0x0 0x58000000 0x0 0x01000000>;
48 interrupts = <GIC_SPI 157 IRQ_ 44 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
49 <GIC_SPI 158 IRQ_ 45 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
50 interrupt-names = "stall", "no 46 interrupt-names = "stall", "nonstall";
51 vdd-supply = <&vdd_gpu>; 47 vdd-supply = <&vdd_gpu>;
52 clocks = <&tegra_car TEGRA124_ 48 clocks = <&tegra_car TEGRA124_CLK_GPU>,
53 <&tegra_car TEGRA124_ 49 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
54 clock-names = "gpu", "pwr"; 50 clock-names = "gpu", "pwr";
55 resets = <&tegra_car 184>; 51 resets = <&tegra_car 184>;
56 reset-names = "gpu"; 52 reset-names = "gpu";
57 iommus = <&mc TEGRA_SWGROUP_GP 53 iommus = <&mc TEGRA_SWGROUP_GPU>;
58 }; 54 };
59 55
60 Example for GM20B: 56 Example for GM20B:
61 57
62 gpu@57000000 { 58 gpu@57000000 {
63 compatible = "nvidia,gm20b"; 59 compatible = "nvidia,gm20b";
64 reg = <0x0 0x57000000 0x0 0x01 60 reg = <0x0 0x57000000 0x0 0x01000000>,
65 <0x0 0x58000000 0x0 0x01 61 <0x0 0x58000000 0x0 0x01000000>;
66 interrupts = <GIC_SPI 157 IRQ_ 62 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_SPI 158 IRQ_ 63 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
68 interrupt-names = "stall", "no 64 interrupt-names = "stall", "nonstall";
69 clocks = <&tegra_car TEGRA210_ 65 clocks = <&tegra_car TEGRA210_CLK_GPU>,
70 <&tegra_car TEGRA210_ 66 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
71 <&tegra_car TEGRA210_ 67 <&tegra_car TEGRA210_CLK_PLL_G_REF>;
72 clock-names = "gpu", "pwr", "r 68 clock-names = "gpu", "pwr", "ref";
73 resets = <&tegra_car 184>; 69 resets = <&tegra_car 184>;
74 reset-names = "gpu"; 70 reset-names = "gpu";
75 iommus = <&mc TEGRA_SWGROUP_GP 71 iommus = <&mc TEGRA_SWGROUP_GPU>;
76 }; 72 };
77 73
78 Example for GP10B: 74 Example for GP10B:
79 75
80 gpu@17000000 { 76 gpu@17000000 {
81 compatible = "nvidia,gp10b"; 77 compatible = "nvidia,gp10b";
82 reg = <0x0 0x17000000 0x0 0x10 78 reg = <0x0 0x17000000 0x0 0x1000000>,
83 <0x0 0x18000000 0x0 0x10 79 <0x0 0x18000000 0x0 0x1000000>;
84 interrupts = <GIC_SPI 70 IRQ_T 80 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
85 GIC_SPI 71 IRQ_T 81 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
86 interrupt-names = "stall", "no 82 interrupt-names = "stall", "nonstall";
87 clocks = <&bpmp TEGRA186_CLK_G 83 clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
88 <&bpmp TEGRA186_CLK_G 84 <&bpmp TEGRA186_CLK_GPU>;
89 clock-names = "gpu", "pwr"; 85 clock-names = "gpu", "pwr";
90 resets = <&bpmp TEGRA186_RESET 86 resets = <&bpmp TEGRA186_RESET_GPU>;
91 reset-names = "gpu"; 87 reset-names = "gpu";
92 power-domains = <&bpmp TEGRA18 88 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
93 iommus = <&smmu TEGRA186_SID_G 89 iommus = <&smmu TEGRA186_SID_GPU>;
94 }; <<
95 <<
96 Example for GV11B: <<
97 <<
98 gpu@17000000 { <<
99 compatible = "nvidia,gv11b"; <<
100 reg = <0x17000000 0x1000000>, <<
101 <0x18000000 0x1000000>; <<
102 interrupts = <GIC_SPI 70 IRQ_T <<
103 <GIC_SPI 71 IRQ_T <<
104 interrupt-names = "stall", "no <<
105 clocks = <&bpmp TEGRA194_CLK_G <<
106 <&bpmp TEGRA194_CLK_G <<
107 <&bpmp TEGRA194_CLK_F <<
108 clock-names = "gpu", "pwr", "f <<
109 resets = <&bpmp TEGRA194_RESET <<
110 reset-names = "gpu"; <<
111 dma-coherent; <<
112 <<
113 power-domains = <&bpmp TEGRA19 <<
114 iommus = <&smmu TEGRA194_SID_G <<
115 }; 90 };
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