1 NVIDIA Tegra Graphics Processing Units 1 NVIDIA Tegra Graphics Processing Units
2 2
3 Required properties: 3 Required properties:
4 - compatible: "nvidia,<gpu>" 4 - compatible: "nvidia,<gpu>"
5 Currently recognized values: 5 Currently recognized values:
6 - nvidia,gk20a 6 - nvidia,gk20a
7 - nvidia,gm20b 7 - nvidia,gm20b
8 - nvidia,gp10b 8 - nvidia,gp10b
9 - nvidia,gv11b 9 - nvidia,gv11b
10 - reg: Physical base address and length of the 10 - reg: Physical base address and length of the controller's registers.
11 Must contain two entries: 11 Must contain two entries:
12 - first entry for bar0 12 - first entry for bar0
13 - second entry for bar1 13 - second entry for bar1
14 - interrupts: Must contain an entry for each e 14 - interrupts: Must contain an entry for each entry in interrupt-names.
15 See ../interrupt-controller/interrupts.txt f 15 See ../interrupt-controller/interrupts.txt for details.
16 - interrupt-names: Must include the following 16 - interrupt-names: Must include the following entries:
17 - stall 17 - stall
18 - nonstall 18 - nonstall
19 - vdd-supply: regulator for supply voltage. On 19 - vdd-supply: regulator for supply voltage. Only required for GPUs not using
20 power domains. 20 power domains.
21 - clocks: Must contain an entry for each entry 21 - clocks: Must contain an entry for each entry in clock-names.
22 See ../clocks/clock-bindings.txt for details 22 See ../clocks/clock-bindings.txt for details.
23 - clock-names: Must include the following entr 23 - clock-names: Must include the following entries:
24 - gpu 24 - gpu
25 - pwr 25 - pwr
26 If the compatible string is "nvidia,gm20b", th 26 If the compatible string is "nvidia,gm20b", then the following clock
27 is also required: 27 is also required:
28 - ref 28 - ref
29 If the compatible string is "nvidia,gv11b", th 29 If the compatible string is "nvidia,gv11b", then the following clock is also
30 required: 30 required:
31 - fuse 31 - fuse
32 - resets: Must contain an entry for each entry 32 - resets: Must contain an entry for each entry in reset-names.
33 See ../reset/reset.txt for details. 33 See ../reset/reset.txt for details.
34 - reset-names: Must include the following entr 34 - reset-names: Must include the following entries:
35 - gpu 35 - gpu
36 - power-domains: GPUs that make use of power d 36 - power-domains: GPUs that make use of power domains can define this property
37 instead of vdd-supply. Currently "nvidia,gp1 37 instead of vdd-supply. Currently "nvidia,gp10b" makes use of this.
38 38
39 Optional properties: 39 Optional properties:
40 - iommus: A reference to the IOMMU. See ../iom 40 - iommus: A reference to the IOMMU. See ../iommu/iommu.txt for details.
41 41
42 Example for GK20A: 42 Example for GK20A:
43 43
44 gpu@57000000 { 44 gpu@57000000 {
45 compatible = "nvidia,gk20a"; 45 compatible = "nvidia,gk20a";
46 reg = <0x0 0x57000000 0x0 0x01 46 reg = <0x0 0x57000000 0x0 0x01000000>,
47 <0x0 0x58000000 0x0 0x01 47 <0x0 0x58000000 0x0 0x01000000>;
48 interrupts = <GIC_SPI 157 IRQ_ 48 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
49 <GIC_SPI 158 IRQ_ 49 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
50 interrupt-names = "stall", "no 50 interrupt-names = "stall", "nonstall";
51 vdd-supply = <&vdd_gpu>; 51 vdd-supply = <&vdd_gpu>;
52 clocks = <&tegra_car TEGRA124_ 52 clocks = <&tegra_car TEGRA124_CLK_GPU>,
53 <&tegra_car TEGRA124_ 53 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
54 clock-names = "gpu", "pwr"; 54 clock-names = "gpu", "pwr";
55 resets = <&tegra_car 184>; 55 resets = <&tegra_car 184>;
56 reset-names = "gpu"; 56 reset-names = "gpu";
57 iommus = <&mc TEGRA_SWGROUP_GP 57 iommus = <&mc TEGRA_SWGROUP_GPU>;
58 }; 58 };
59 59
60 Example for GM20B: 60 Example for GM20B:
61 61
62 gpu@57000000 { 62 gpu@57000000 {
63 compatible = "nvidia,gm20b"; 63 compatible = "nvidia,gm20b";
64 reg = <0x0 0x57000000 0x0 0x01 64 reg = <0x0 0x57000000 0x0 0x01000000>,
65 <0x0 0x58000000 0x0 0x01 65 <0x0 0x58000000 0x0 0x01000000>;
66 interrupts = <GIC_SPI 157 IRQ_ 66 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_SPI 158 IRQ_ 67 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
68 interrupt-names = "stall", "no 68 interrupt-names = "stall", "nonstall";
69 clocks = <&tegra_car TEGRA210_ 69 clocks = <&tegra_car TEGRA210_CLK_GPU>,
70 <&tegra_car TEGRA210_ 70 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
71 <&tegra_car TEGRA210_ 71 <&tegra_car TEGRA210_CLK_PLL_G_REF>;
72 clock-names = "gpu", "pwr", "r 72 clock-names = "gpu", "pwr", "ref";
73 resets = <&tegra_car 184>; 73 resets = <&tegra_car 184>;
74 reset-names = "gpu"; 74 reset-names = "gpu";
75 iommus = <&mc TEGRA_SWGROUP_GP 75 iommus = <&mc TEGRA_SWGROUP_GPU>;
76 }; 76 };
77 77
78 Example for GP10B: 78 Example for GP10B:
79 79
80 gpu@17000000 { 80 gpu@17000000 {
81 compatible = "nvidia,gp10b"; 81 compatible = "nvidia,gp10b";
82 reg = <0x0 0x17000000 0x0 0x10 82 reg = <0x0 0x17000000 0x0 0x1000000>,
83 <0x0 0x18000000 0x0 0x10 83 <0x0 0x18000000 0x0 0x1000000>;
84 interrupts = <GIC_SPI 70 IRQ_T 84 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
85 GIC_SPI 71 IRQ_T 85 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
86 interrupt-names = "stall", "no 86 interrupt-names = "stall", "nonstall";
87 clocks = <&bpmp TEGRA186_CLK_G 87 clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
88 <&bpmp TEGRA186_CLK_G 88 <&bpmp TEGRA186_CLK_GPU>;
89 clock-names = "gpu", "pwr"; 89 clock-names = "gpu", "pwr";
90 resets = <&bpmp TEGRA186_RESET 90 resets = <&bpmp TEGRA186_RESET_GPU>;
91 reset-names = "gpu"; 91 reset-names = "gpu";
92 power-domains = <&bpmp TEGRA18 92 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
93 iommus = <&smmu TEGRA186_SID_G 93 iommus = <&smmu TEGRA186_SID_GPU>;
94 }; 94 };
95 95
96 Example for GV11B: 96 Example for GV11B:
97 97
98 gpu@17000000 { 98 gpu@17000000 {
99 compatible = "nvidia,gv11b"; 99 compatible = "nvidia,gv11b";
100 reg = <0x17000000 0x1000000>, !! 100 reg = <0x17000000 0x10000000>,
101 <0x18000000 0x1000000>; !! 101 <0x18000000 0x10000000>;
102 interrupts = <GIC_SPI 70 IRQ_T 102 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 71 IRQ_T 103 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
104 interrupt-names = "stall", "no 104 interrupt-names = "stall", "nonstall";
105 clocks = <&bpmp TEGRA194_CLK_G 105 clocks = <&bpmp TEGRA194_CLK_GPCCLK>,
106 <&bpmp TEGRA194_CLK_G 106 <&bpmp TEGRA194_CLK_GPU_PWR>,
107 <&bpmp TEGRA194_CLK_F 107 <&bpmp TEGRA194_CLK_FUSE>;
108 clock-names = "gpu", "pwr", "f 108 clock-names = "gpu", "pwr", "fuse";
109 resets = <&bpmp TEGRA194_RESET 109 resets = <&bpmp TEGRA194_RESET_GPU>;
110 reset-names = "gpu"; 110 reset-names = "gpu";
111 dma-coherent; 111 dma-coherent;
112 112
113 power-domains = <&bpmp TEGRA19 113 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
114 iommus = <&smmu TEGRA194_SID_G 114 iommus = <&smmu TEGRA194_SID_GPU>;
115 }; 115 };
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