1 OMAP SSI controller bindings 1 OMAP SSI controller bindings
2 2
3 OMAP3's Synchronous Serial Interface (SSI) con !! 3 OMAP Synchronous Serial Interface (SSI) controller implements a legacy
4 legacy variant of MIPI's High Speed Synchronou !! 4 variant of MIPI's High Speed Synchronous Serial Interface (HSI).
5 while the controller found inside OMAP4 is sup <<
6 with the HSI standard. <<
7 5
8 Required properties: 6 Required properties:
9 - compatible: Should include "ti,oma !! 7 - compatible: Should include "ti,omap3-ssi".
10 - reg-names: Contains the values "s 8 - reg-names: Contains the values "sys" and "gdd" (in this order).
11 - reg: Contains a matching re 9 - reg: Contains a matching register specifier for each entry
12 in reg-names. 10 in reg-names.
13 - interrupt-names: Contains the value "gd 11 - interrupt-names: Contains the value "gdd_mpu".
14 - interrupts: Contains matching inte 12 - interrupts: Contains matching interrupt information for each entry
15 in interrupt-names. 13 in interrupt-names.
16 - ranges: Represents the bus add 14 - ranges: Represents the bus address mapping between the main
17 controller node and th 15 controller node and the child nodes below.
18 - clock-names: Must include the follo 16 - clock-names: Must include the following entries:
19 "ssi_ssr_fck": The OMAP clock of that name 17 "ssi_ssr_fck": The OMAP clock of that name
20 "ssi_sst_fck": The OMAP clock of that name 18 "ssi_sst_fck": The OMAP clock of that name
21 "ssi_ick": The OMAP clock of that name 19 "ssi_ick": The OMAP clock of that name
22 - clocks: Contains a matching cl 20 - clocks: Contains a matching clock specifier for each entry in
23 clock-names. 21 clock-names.
24 - #address-cells: Should be set to <1> 22 - #address-cells: Should be set to <1>
25 - #size-cells: Should be set to <1> 23 - #size-cells: Should be set to <1>
26 24
27 Each port is represented as a sub-node of the 25 Each port is represented as a sub-node of the ti,omap3-ssi device.
28 26
29 Required Port sub-node properties: 27 Required Port sub-node properties:
30 - compatible: Should be set to the f 28 - compatible: Should be set to the following value
31 ti,omap3-ssi-port (app 29 ti,omap3-ssi-port (applicable to OMAP34xx devices)
32 ti,omap4-hsi-port (app <<
33 - reg-names: Contains the values "t 30 - reg-names: Contains the values "tx" and "rx" (in this order).
34 - reg: Contains a matching re 31 - reg: Contains a matching register specifier for each entry
35 in reg-names. 32 in reg-names.
>> 33 - interrupt-parent Should be a phandle for the interrupt controller
36 - interrupts: Should contain interru 34 - interrupts: Should contain interrupt specifiers for mpu interrupts
37 0 and 1 (in this order 35 0 and 1 (in this order).
38 - ti,ssi-cawake-gpio: Defines which GPIO pin 36 - ti,ssi-cawake-gpio: Defines which GPIO pin is used to signify CAWAKE
39 events for the port. T 37 events for the port. This is an optional board-specific
40 property. If it's miss 38 property. If it's missing the port will not be
41 enabled. 39 enabled.
42 40
43 Optional properties: <<
44 - ti,hwmods: Shall contain TI inter <<
45 by the SoC <<
46 <<
47 Example for Nokia N900: 41 Example for Nokia N900:
48 42
49 ssi-controller@48058000 { 43 ssi-controller@48058000 {
50 compatible = "ti,omap3-ssi"; 44 compatible = "ti,omap3-ssi";
51 45
52 /* needed until hwmod is updated to us 46 /* needed until hwmod is updated to use the compatible string */
53 ti,hwmods = "ssi"; 47 ti,hwmods = "ssi";
54 48
55 reg = <0x48058000 0x1000>, 49 reg = <0x48058000 0x1000>,
56 <0x48059000 0x1000>; 50 <0x48059000 0x1000>;
57 reg-names = "sys", 51 reg-names = "sys",
58 "gdd"; 52 "gdd";
59 53
60 interrupts = <55>; 54 interrupts = <55>;
61 interrupt-names = "gdd_mpu"; 55 interrupt-names = "gdd_mpu";
62 56
63 clocks = <&ssi_ssr_fck>, 57 clocks = <&ssi_ssr_fck>,
64 <&ssi_sst_fck>, 58 <&ssi_sst_fck>,
65 <&ssi_ick>; 59 <&ssi_ick>;
66 clock-names = "ssi_ssr_fck", 60 clock-names = "ssi_ssr_fck",
67 "ssi_sst_fck", 61 "ssi_sst_fck",
68 "ssi_ick"; 62 "ssi_ick";
69 63
70 #address-cells = <1>; 64 #address-cells = <1>;
71 #size-cells = <1>; 65 #size-cells = <1>;
72 ranges; 66 ranges;
73 67
74 ssi-port@4805a000 { 68 ssi-port@4805a000 {
75 compatible = "ti,omap3-ssi-por 69 compatible = "ti,omap3-ssi-port";
76 70
77 reg = <0x4805a000 0x800>, 71 reg = <0x4805a000 0x800>,
78 <0x4805a800 0x800>; 72 <0x4805a800 0x800>;
79 reg-names = "tx", 73 reg-names = "tx",
80 "rx"; 74 "rx";
81 75
82 interrupt-parent = <&intc>; 76 interrupt-parent = <&intc>;
83 interrupts = <67>, 77 interrupts = <67>,
84 <68>; 78 <68>;
85 79
86 ti,ssi-cawake-gpio = <&gpio5 2 80 ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */
87 } 81 }
88 82
89 ssi-port@4805a000 { 83 ssi-port@4805a000 {
90 compatible = "ti,omap3-ssi-por 84 compatible = "ti,omap3-ssi-port";
91 85
92 reg = <0x4805b000 0x800>, 86 reg = <0x4805b000 0x800>,
93 <0x4805b800 0x800>; 87 <0x4805b800 0x800>;
94 reg-names = "tx", 88 reg-names = "tx",
95 "rx"; 89 "rx";
96 90
97 interrupt-parent = <&intc>; 91 interrupt-parent = <&intc>;
98 interrupts = <69>, 92 interrupts = <69>,
99 <70>; 93 <70>;
100 94
>> 95 status = "disabled"; /* second port is not used on N900 */
101 } 96 }
102 } 97 }
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