1 # SPDX-License-Identifier: GPL-2.0 1 # SPDX-License-Identifier: GPL-2.0
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-mux 4 $id: http://devicetree.org/schemas/i2c/i2c-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Common i2c bus multiplexer/switch prope 7 title: Common i2c bus multiplexer/switch properties.
8 8
9 maintainers: 9 maintainers:
10 - Peter Rosin <peda@axentia.se> 10 - Peter Rosin <peda@axentia.se>
11 11
12 description: |+ 12 description: |+
13 An i2c bus multiplexer/switch will have seve 13 An i2c bus multiplexer/switch will have several child busses that are numbered
14 uniquely in a device dependent manner. The 14 uniquely in a device dependent manner. The nodes for an i2c bus
15 multiplexer/switch will have one child node 15 multiplexer/switch will have one child node for each child bus.
16 16
17 For i2c multiplexers/switches that have chil 17 For i2c multiplexers/switches that have child nodes that are a mixture of both
18 i2c child busses and other child nodes, the 18 i2c child busses and other child nodes, the 'i2c-mux' subnode can be used for
19 populating the i2c child busses. If an 'i2c 19 populating the i2c child busses. If an 'i2c-mux' subnode is present, only
20 subnodes of this will be considered as i2c c 20 subnodes of this will be considered as i2c child busses.
21 21
22 properties: 22 properties:
23 $nodename: 23 $nodename:
24 pattern: '^(i2c-?)?mux' 24 pattern: '^(i2c-?)?mux'
25 25
26 '#address-cells': 26 '#address-cells':
27 const: 1 27 const: 1
28 28
29 '#size-cells': 29 '#size-cells':
30 const: 0 30 const: 0
31 31
32 patternProperties: 32 patternProperties:
33 '^i2c@[0-9a-f]+$': 33 '^i2c@[0-9a-f]+$':
34 $ref: /schemas/i2c/i2c-controller.yaml 34 $ref: /schemas/i2c/i2c-controller.yaml
35 unevaluatedProperties: false 35 unevaluatedProperties: false
36 36
37 properties: 37 properties:
38 reg: 38 reg:
39 description: The mux selector sub-bus 39 description: The mux selector sub-bus number for the child I2C bus.
40 maxItems: 1 40 maxItems: 1
41 41
42 additionalProperties: true 42 additionalProperties: true
43 43
44 examples: 44 examples:
45 - | 45 - |
46 /* 46 /*
47 * An NXP pca9548 8 channel I2C multiplexe 47 * An NXP pca9548 8 channel I2C multiplexer at address 0x70
48 * with two NXP pca8574 GPIO expanders att 48 * with two NXP pca8574 GPIO expanders attached, one each to
49 * ports 3 and 4. 49 * ports 3 and 4.
50 */ 50 */
51 i2c { 51 i2c {
52 #address-cells = <1>; 52 #address-cells = <1>;
53 #size-cells = <0>; 53 #size-cells = <0>;
54 54
55 i2c-mux@70 { 55 i2c-mux@70 {
56 compatible = "nxp,pca9548"; 56 compatible = "nxp,pca9548";
57 reg = <0x70>; 57 reg = <0x70>;
58 #address-cells = <1>; 58 #address-cells = <1>;
59 #size-cells = <0>; 59 #size-cells = <0>;
60 60
61 i2c@3 { 61 i2c@3 {
62 #address-cells = <1>; 62 #address-cells = <1>;
63 #size-cells = <0>; 63 #size-cells = <0>;
64 reg = <3>; 64 reg = <3>;
65 65
66 gpio@20 { 66 gpio@20 {
67 compatible = "nxp,pca9555" 67 compatible = "nxp,pca9555";
68 gpio-controller; 68 gpio-controller;
69 #gpio-cells = <2>; 69 #gpio-cells = <2>;
70 reg = <0x20>; 70 reg = <0x20>;
71 }; 71 };
72 }; 72 };
73 i2c@4 { 73 i2c@4 {
74 #address-cells = <1>; 74 #address-cells = <1>;
75 #size-cells = <0>; 75 #size-cells = <0>;
76 reg = <4>; 76 reg = <4>;
77 77
78 gpio@20 { 78 gpio@20 {
79 compatible = "nxp,pca9555" 79 compatible = "nxp,pca9555";
80 gpio-controller; 80 gpio-controller;
81 #gpio-cells = <2>; 81 #gpio-cells = <2>;
82 reg = <0x20>; 82 reg = <0x20>;
83 }; 83 };
84 }; 84 };
85 }; 85 };
86 }; 86 };
87 ... 87 ...
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