1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-C 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/iio/adc/fsl 4 $id: http://devicetree.org/schemas/iio/adc/fsl,vf610-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: ADC found on Freescale vf610 and simila 7 title: ADC found on Freescale vf610 and similar SoCs
8 8
9 maintainers: 9 maintainers:
10 - Haibo Chen <haibo.chen@nxp.com> 10 - Haibo Chen <haibo.chen@nxp.com>
11 11
12 description: 12 description:
13 ADCs found on vf610/i.MX6slx and upward SoCs 13 ADCs found on vf610/i.MX6slx and upward SoCs from Freescale.
14 14
15 properties: 15 properties:
16 compatible: 16 compatible:
17 oneOf: 17 oneOf:
18 - items: 18 - items:
19 - enum: 19 - enum:
20 - fsl,imx6sx-adc 20 - fsl,imx6sx-adc
21 - fsl,imx6ul-adc 21 - fsl,imx6ul-adc
22 - const: fsl,vf610-adc 22 - const: fsl,vf610-adc
23 - items: 23 - items:
24 - const: fsl,vf610-adc 24 - const: fsl,vf610-adc
25 25
26 reg: 26 reg:
27 maxItems: 1 27 maxItems: 1
28 28
29 interrupts: 29 interrupts:
30 maxItems: 1 30 maxItems: 1
31 31
32 clocks: 32 clocks:
33 description: ADC source clock (ipg clock) 33 description: ADC source clock (ipg clock)
34 maxItems: 1 34 maxItems: 1
35 35
36 clock-names: 36 clock-names:
37 const: adc 37 const: adc
38 38
39 vref-supply: 39 vref-supply:
40 description: ADC reference voltage supply. 40 description: ADC reference voltage supply.
41 41
42 fsl,adck-max-frequency: 42 fsl,adck-max-frequency:
43 $ref: /schemas/types.yaml#/definitions/uin 43 $ref: /schemas/types.yaml#/definitions/uint32-array
44 minItems: 3 44 minItems: 3
45 maxItems: 3 45 maxItems: 3
46 description: | 46 description: |
47 Maximum frequencies from datasheet opera 47 Maximum frequencies from datasheet operating requirements.
48 Three values necessary to cover the 3 co 48 Three values necessary to cover the 3 conversion modes.
49 * Frequency in normal mode (ADLPC=0, ADH 49 * Frequency in normal mode (ADLPC=0, ADHSC=0)
50 * Frequency in high-speed mode (ADLPC=0, 50 * Frequency in high-speed mode (ADLPC=0, ADHSC=1)
51 * Frequency in low-power mode (ADLPC=1, 51 * Frequency in low-power mode (ADLPC=1, ADHSC=0)
52 52
53 min-sample-time: 53 min-sample-time:
54 $ref: /schemas/types.yaml#/definitions/uin 54 $ref: /schemas/types.yaml#/definitions/uint32
55 description: 55 description:
56 Minimum sampling time in nanoseconds. Th 56 Minimum sampling time in nanoseconds. This value has
57 to be chosen according to the conversion 57 to be chosen according to the conversion mode and the connected analog
58 source resistance (R_as) and capacitance 58 source resistance (R_as) and capacitance (C_as). Refer the datasheet's
59 operating requirements. A safe default a 59 operating requirements. A safe default across a wide range of R_as and
60 C_as as well as conversion modes is 1000 60 C_as as well as conversion modes is 1000ns.
61 61
62 "#io-channel-cells": 62 "#io-channel-cells":
63 const: 1 63 const: 1
64 64
65 required: 65 required:
66 - compatible 66 - compatible
67 - reg 67 - reg
68 - interrupts 68 - interrupts
69 - clocks 69 - clocks
70 - clock-names 70 - clock-names
71 - vref-supply 71 - vref-supply
72 72
73 additionalProperties: false 73 additionalProperties: false
74 74
75 examples: 75 examples:
76 - | 76 - |
77 #include <dt-bindings/clock/vf610-clock.h> 77 #include <dt-bindings/clock/vf610-clock.h>
78 adc@4003b000 { 78 adc@4003b000 {
79 compatible = "fsl,vf610-adc"; 79 compatible = "fsl,vf610-adc";
80 reg = <0x4003b000 0x1000>; 80 reg = <0x4003b000 0x1000>;
81 interrupts = <0 53 0x04>; 81 interrupts = <0 53 0x04>;
82 clocks = <&clks VF610_CLK_ADC0>; 82 clocks = <&clks VF610_CLK_ADC0>;
83 clock-names = "adc"; 83 clock-names = "adc";
84 fsl,adck-max-frequency = <30000000>, < 84 fsl,adck-max-frequency = <30000000>, <40000000>, <20000000>;
85 vref-supply = <®_vcc_3v3_mcu>; 85 vref-supply = <®_vcc_3v3_mcu>;
86 min-sample-time = <10000>; 86 min-sample-time = <10000>;
87 }; 87 };
88 ... 88 ...
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