1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/iio/adc/ren 4 $id: http://devicetree.org/schemas/iio/adc/renesas,rzg2l-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Renesas RZ/G2L ADC 7 title: Renesas RZ/G2L ADC
8 8
9 maintainers: 9 maintainers:
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp. 10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
11 11
12 description: | 12 description: |
13 A/D Converter block is a successive approxim 13 A/D Converter block is a successive approximation analog-to-digital converter
14 with a 12-bit accuracy. Up to eight analog i 14 with a 12-bit accuracy. Up to eight analog input channels can be selected.
15 Conversions can be performed in single or re 15 Conversions can be performed in single or repeat mode. Result of the ADC is
16 stored in a 32-bit data register correspondi 16 stored in a 32-bit data register corresponding to each channel.
17 17
18 properties: 18 properties:
19 compatible: 19 compatible:
20 items: 20 items:
21 - enum: 21 - enum:
22 - renesas,r9a07g043-adc # RZ/G2UL 22 - renesas,r9a07g043-adc # RZ/G2UL and RZ/Five
23 - renesas,r9a07g044-adc # RZ/G2L 23 - renesas,r9a07g044-adc # RZ/G2L
24 - renesas,r9a07g054-adc # RZ/V2L 24 - renesas,r9a07g054-adc # RZ/V2L
25 - const: renesas,rzg2l-adc 25 - const: renesas,rzg2l-adc
26 26
27 reg: 27 reg:
28 maxItems: 1 28 maxItems: 1
29 29
30 interrupts: 30 interrupts:
31 maxItems: 1 31 maxItems: 1
32 32
33 clocks: 33 clocks:
34 items: 34 items:
35 - description: converter clock 35 - description: converter clock
36 - description: peripheral clock 36 - description: peripheral clock
37 37
38 clock-names: 38 clock-names:
39 items: 39 items:
40 - const: adclk 40 - const: adclk
41 - const: pclk 41 - const: pclk
42 42
43 power-domains: 43 power-domains:
44 maxItems: 1 44 maxItems: 1
45 45
46 resets: 46 resets:
47 maxItems: 2 47 maxItems: 2
48 48
49 reset-names: 49 reset-names:
50 items: 50 items:
51 - const: presetn 51 - const: presetn
52 - const: adrst-n 52 - const: adrst-n
53 53
54 '#address-cells': 54 '#address-cells':
55 const: 1 55 const: 1
56 56
57 '#size-cells': 57 '#size-cells':
58 const: 0 58 const: 0
59 59
60 required: 60 required:
61 - compatible 61 - compatible
62 - reg 62 - reg
63 - interrupts 63 - interrupts
64 - clocks 64 - clocks
65 - clock-names 65 - clock-names
66 - power-domains 66 - power-domains
67 - resets 67 - resets
68 - reset-names 68 - reset-names
69 69
70 patternProperties: 70 patternProperties:
71 "^channel@[0-7]$": 71 "^channel@[0-7]$":
72 $ref: adc.yaml 72 $ref: adc.yaml
73 type: object 73 type: object
74 description: | 74 description: |
75 Represents the external channels which a 75 Represents the external channels which are connected to the ADC.
76 76
77 properties: 77 properties:
78 reg: 78 reg:
79 description: | 79 description: |
80 The channel number. 80 The channel number.
81 81
82 required: 82 required:
83 - reg 83 - reg
84 84
85 additionalProperties: false 85 additionalProperties: false
86 86
87 allOf: 87 allOf:
88 - if: 88 - if:
89 properties: 89 properties:
90 compatible: 90 compatible:
91 contains: 91 contains:
92 const: renesas,r9a07g043-adc 92 const: renesas,r9a07g043-adc
93 then: 93 then:
94 patternProperties: 94 patternProperties:
95 "^channel@[2-7]$": false 95 "^channel@[2-7]$": false
96 "^channel@[0-1]$": 96 "^channel@[0-1]$":
97 properties: 97 properties:
98 reg: 98 reg:
99 minimum: 0 99 minimum: 0
100 maximum: 1 100 maximum: 1
101 else: 101 else:
102 patternProperties: 102 patternProperties:
103 "^channel@[0-7]$": 103 "^channel@[0-7]$":
104 properties: 104 properties:
105 reg: 105 reg:
106 minimum: 0 106 minimum: 0
107 maximum: 7 107 maximum: 7
108 108
109 additionalProperties: false 109 additionalProperties: false
110 110
111 examples: 111 examples:
112 - | 112 - |
113 #include <dt-bindings/clock/r9a07g044-cpg. 113 #include <dt-bindings/clock/r9a07g044-cpg.h>
114 #include <dt-bindings/interrupt-controller 114 #include <dt-bindings/interrupt-controller/arm-gic.h>
115 115
116 adc: adc@10059000 { 116 adc: adc@10059000 {
117 compatible = "renesas,r9a07g044-adc", "r 117 compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc";
118 reg = <0x10059000 0x400>; 118 reg = <0x10059000 0x400>;
119 interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_ 119 interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
120 clocks = <&cpg CPG_MOD R9A07G044_ADC_ADC 120 clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,
121 <&cpg CPG_MOD R9A07G044_ADC_PCL 121 <&cpg CPG_MOD R9A07G044_ADC_PCLK>;
122 clock-names = "adclk", "pclk"; 122 clock-names = "adclk", "pclk";
123 power-domains = <&cpg>; 123 power-domains = <&cpg>;
124 resets = <&cpg R9A07G044_ADC_PRESETN>, 124 resets = <&cpg R9A07G044_ADC_PRESETN>,
125 <&cpg R9A07G044_ADC_ADRST_N>; 125 <&cpg R9A07G044_ADC_ADRST_N>;
126 reset-names = "presetn", "adrst-n"; 126 reset-names = "presetn", "adrst-n";
127 127
128 #address-cells = <1>; 128 #address-cells = <1>;
129 #size-cells = <0>; 129 #size-cells = <0>;
130 130
131 channel@0 { 131 channel@0 {
132 reg = <0>; 132 reg = <0>;
133 }; 133 };
134 channel@1 { 134 channel@1 {
135 reg = <1>; 135 reg = <1>;
136 }; 136 };
137 channel@2 { 137 channel@2 {
138 reg = <2>; 138 reg = <2>;
139 }; 139 };
140 channel@3 { 140 channel@3 {
141 reg = <3>; 141 reg = <3>;
142 }; 142 };
143 channel@4 { 143 channel@4 {
144 reg = <4>; 144 reg = <4>;
145 }; 145 };
146 channel@5 { 146 channel@5 {
147 reg = <5>; 147 reg = <5>;
148 }; 148 };
149 channel@6 { 149 channel@6 {
150 reg = <6>; 150 reg = <6>;
151 }; 151 };
152 channel@7 { 152 channel@7 {
153 reg = <7>; 153 reg = <7>;
154 }; 154 };
155 }; 155 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.