1 # SPDX-License-Identifier: GPL-2.0
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/interconnec
5 $schema: http://devicetree.org/meta-schemas/co
6
7 title: Generic i.MX bus frequency device
8
9 maintainers:
10 - Peng Fan <peng.fan@nxp.com>
11
12 description: |
13 The i.MX SoC family has multiple buses for w
14 sometimes voltage) can be adjusted.
15
16 Some of those buses expose register areas me
17 ("Global Programmers View") but not all. Acc
18 for normal (non-secure) world.
19
20 The buses are based on externally licensed I
21 Arteris FlexNOC but DT bindings are specific
22 interconnect IPs into imx SOCs.
23
24 properties:
25 compatible:
26 oneOf:
27 - items:
28 - enum:
29 - fsl,imx8mm-nic
30 - fsl,imx8mn-nic
31 - fsl,imx8mp-nic
32 - fsl,imx8mq-nic
33 - const: fsl,imx8m-nic
34 - items:
35 - enum:
36 - fsl,imx8mm-noc
37 - fsl,imx8mn-noc
38 - fsl,imx8mp-noc
39 - fsl,imx8mq-noc
40 - const: fsl,imx8m-noc
41 - const: fsl,imx8m-nic
42
43 reg:
44 maxItems: 1
45
46 clocks:
47 maxItems: 1
48
49 operating-points-v2: true
50 opp-table:
51 type: object
52
53 fsl,ddrc:
54 $ref: /schemas/types.yaml#/definitions/pha
55 description:
56 Phandle to DDR Controller.
57
58 '#interconnect-cells':
59 description:
60 If specified then also act as an interco
61 set once per soc on the main noc.
62 const: 1
63
64 required:
65 - compatible
66 - clocks
67
68 additionalProperties: false
69
70 examples:
71 - |
72 #include <dt-bindings/clock/imx8mm-clock.h
73 #include <dt-bindings/interconnect/imx8mm.
74 #include <dt-bindings/interrupt-controller
75
76 noc: interconnect@32700000 {
77 compatible = "fsl,imx8mm-noc", "fsl,im
78 reg = <0x32700000 0x100000>;
79 clocks = <&clk IMX8MM_CLK_NOC>;
80 #interconnect-cells = <1>;
81 fsl,ddrc = <&ddrc>;
82
83 operating-points-v2 = <&noc_opp_table>
84 noc_opp_table: opp-table {
85 compatible = "operating-points-v2"
86
87 opp-133333333 {
88 opp-hz = /bits/ 64 <133333333>
89 };
90 opp-800000000 {
91 opp-hz = /bits/ 64 <800000000>
92 };
93 };
94 };
95
96 ddrc: memory-controller@3d400000 {
97 compatible = "fsl,imx8mm-ddrc", "fsl,i
98 reg = <0x3d400000 0x400000>;
99 clock-names = "core", "pll", "alt", "a
100 clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
101 <&clk IMX8MM_DRAM_PLL>,
102 <&clk IMX8MM_CLK_DRAM_ALT>,
103 <&clk IMX8MM_CLK_DRAM_APB>;
104 };
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