1 # SPDX-License-Identifier: GPL-2.0 1 # SPDX-License-Identifier: GPL-2.0
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/interrupt-c 4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: ARM Generic Interrupt Controller, versi 7 title: ARM Generic Interrupt Controller, version 3
8 8
9 maintainers: 9 maintainers:
10 - Marc Zyngier <maz@kernel.org> !! 10 - Marc Zyngier <marc.zyngier@arm.com>
11 11
12 description: | 12 description: |
13 AArch64 SMP cores are often associated with 13 AArch64 SMP cores are often associated with a GICv3, providing Private
14 Peripheral Interrupts (PPI), Shared Peripher 14 Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI),
15 Software Generated Interrupts (SGI), and Loc 15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
16 Interrupts (LPI). 16 Interrupts (LPI).
17 17
18 allOf: 18 allOf:
19 - $ref: /schemas/interrupt-controller.yaml# 19 - $ref: /schemas/interrupt-controller.yaml#
20 20
21 properties: 21 properties:
22 compatible: 22 compatible:
23 oneOf: 23 oneOf:
24 - items: 24 - items:
25 - enum: 25 - enum:
26 - qcom,msm8996-gic-v3 26 - qcom,msm8996-gic-v3
27 - const: arm,gic-v3 27 - const: arm,gic-v3
28 - const: arm,gic-v3 28 - const: arm,gic-v3
29 29
30 interrupt-controller: true 30 interrupt-controller: true
31 31
32 "#address-cells": 32 "#address-cells":
33 enum: [ 0, 1, 2 ] 33 enum: [ 0, 1, 2 ]
34 "#size-cells": 34 "#size-cells":
35 enum: [ 1, 2 ] 35 enum: [ 1, 2 ]
36 36
37 ranges: true 37 ranges: true
38 38
39 "#interrupt-cells": 39 "#interrupt-cells":
40 description: | 40 description: |
41 Specifies the number of cells needed to 41 Specifies the number of cells needed to encode an interrupt source.
42 Must be a single cell with a value of at 42 Must be a single cell with a value of at least 3.
43 If the system requires describing PPI af 43 If the system requires describing PPI affinity, then the value must
44 be at least 4. 44 be at least 4.
45 45
46 The 1st cell is the interrupt type; 0 fo 46 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
47 interrupts, 2 for interrupts in the Exte !! 47 interrupts. Other values are reserved for future use.
48 Extended PPI range. Other values are res <<
49 48
50 The 2nd cell contains the interrupt numb 49 The 2nd cell contains the interrupt number for the interrupt type.
51 SPI interrupts are in the range [0-987]. 50 SPI interrupts are in the range [0-987]. PPI interrupts are in the
52 range [0-15]. Extended SPI interrupts ar !! 51 range [0-15].
53 Extended PPI interrupts are in the range <<
54 52
55 The 3rd cell is the flags, encoded as fo 53 The 3rd cell is the flags, encoded as follows:
56 bits[3:0] trigger type and level flags. 54 bits[3:0] trigger type and level flags.
57 1 = edge triggered 55 1 = edge triggered
58 4 = level triggered 56 4 = level triggered
59 57
60 The 4th cell is a phandle to a node desc 58 The 4th cell is a phandle to a node describing a set of CPUs this
61 interrupt is affine to. The interrupt mu 59 interrupt is affine to. The interrupt must be a PPI, and the node
62 pointed must be a subnode of the "ppi-pa 60 pointed must be a subnode of the "ppi-partitions" subnode. For
63 interrupt types other than PPI or PPIs t !! 61 interrupt types other than PPI or PPIs that are not partitionned,
64 this cell must be zero. See the "ppi-par 62 this cell must be zero. See the "ppi-partitions" node description
65 below. 63 below.
66 64
67 Cells 5 and beyond are reserved for futu 65 Cells 5 and beyond are reserved for future use and must have a value
68 of 0 if present. 66 of 0 if present.
69 enum: [ 3, 4 ] 67 enum: [ 3, 4 ]
70 68
71 reg: 69 reg:
72 description: | 70 description: |
73 Specifies base physical address(s) and s 71 Specifies base physical address(s) and size of the GIC
74 registers, in the following order: 72 registers, in the following order:
75 - GIC Distributor interface (GICD) 73 - GIC Distributor interface (GICD)
76 - GIC Redistributors (GICR), one range p 74 - GIC Redistributors (GICR), one range per redistributor region
77 - GIC CPU interface (GICC) 75 - GIC CPU interface (GICC)
78 - GIC Hypervisor interface (GICH) 76 - GIC Hypervisor interface (GICH)
79 - GIC Virtual CPU interface (GICV) 77 - GIC Virtual CPU interface (GICV)
80 78
81 GICC, GICH and GICV are optional, but mu !! 79 GICC, GICH and GICV are optional.
82 support them. Examples of such CPUs are <<
83 ARMv8.0 architecture such as Cortex-A32, <<
84 A73 (this list is not exhaustive). <<
85 <<
86 minItems: 2 80 minItems: 2
87 maxItems: 4096 # Should be enough? 81 maxItems: 4096 # Should be enough?
88 82
89 interrupts: 83 interrupts:
90 description: 84 description:
91 Interrupt source of the VGIC maintenance 85 Interrupt source of the VGIC maintenance interrupt.
92 maxItems: 1 86 maxItems: 1
93 87
94 redistributor-stride: 88 redistributor-stride:
95 description: 89 description:
96 If using padding pages, specifies the st 90 If using padding pages, specifies the stride of consecutive
97 redistributors. Must be a multiple of 64 91 redistributors. Must be a multiple of 64kB.
98 $ref: /schemas/types.yaml#/definitions/uin !! 92 allOf:
99 multipleOf: 0x10000 !! 93 - $ref: /schemas/types.yaml#/definitions/uint64
100 exclusiveMinimum: 0 !! 94 - multipleOf: 0x10000
>> 95 exclusiveMinimum: 0
101 96
102 "#redistributor-regions": 97 "#redistributor-regions":
103 description: 98 description:
104 The number of independent contiguous reg 99 The number of independent contiguous regions occupied by the
105 redistributors. Required if more than on 100 redistributors. Required if more than one such region is present.
106 $ref: /schemas/types.yaml#/definitions/uin !! 101 allOf:
107 maximum: 4096 !! 102 - $ref: /schemas/types.yaml#/definitions/uint32
108 !! 103 - maximum: 4096 # Should be enough?
109 dma-noncoherent: <<
110 description: <<
111 Present if the GIC redistributors permit <<
112 and cacheability attributes but are conn <<
113 downstream interconnect. <<
114 104
115 msi-controller: 105 msi-controller:
116 description: 106 description:
117 Only present if the Message Based Interr !! 107 Only present if the Message Based Interrupt functionnality is
118 being exposed by the HW, and the mbi-ran 108 being exposed by the HW, and the mbi-ranges property present.
119 109
120 mbi-ranges: 110 mbi-ranges:
121 description: 111 description:
122 A list of pairs <intid span>, where "int 112 A list of pairs <intid span>, where "intid" is the first SPI of a range
123 that can be used an MBI, and "span" the 113 that can be used an MBI, and "span" the size of that range. Multiple
124 ranges can be provided. 114 ranges can be provided.
125 $ref: /schemas/types.yaml#/definitions/uin !! 115 allOf:
126 items: !! 116 - $ref: /schemas/types.yaml#/definitions/uint32-matrix
127 minItems: 2 !! 117 - items:
128 maxItems: 2 !! 118 minItems: 2
>> 119 maxItems: 2
129 120
130 mbi-alias: 121 mbi-alias:
131 description: 122 description:
132 Address property. Base address of an ali 123 Address property. Base address of an alias of the GICD region containing
133 only the {SET,CLR}SPI registers to be us 124 only the {SET,CLR}SPI registers to be used if isolation is required,
134 and if supported by the HW. 125 and if supported by the HW.
135 $ref: /schemas/types.yaml#/definitions/uin !! 126 allOf:
136 items: !! 127 - $ref: /schemas/types.yaml#/definitions/uint32-array
137 minItems: 1 !! 128 - items:
138 maxItems: 2 !! 129 minItems: 1
>> 130 maxItems: 2
139 131
140 ppi-partitions: 132 ppi-partitions:
141 type: object 133 type: object
142 additionalProperties: false <<
143 description: 134 description:
144 PPI affinity can be expressed as a singl 135 PPI affinity can be expressed as a single "ppi-partitions" node,
145 containing a set of sub-nodes. 136 containing a set of sub-nodes.
146 patternProperties: 137 patternProperties:
147 "^interrupt-partition-[0-9]+$": 138 "^interrupt-partition-[0-9]+$":
148 type: object <<
149 additionalProperties: false <<
150 properties: 139 properties:
151 affinity: 140 affinity:
152 $ref: /schemas/types.yaml#/definit 141 $ref: /schemas/types.yaml#/definitions/phandle-array
153 items: <<
154 maxItems: 1 <<
155 description: 142 description:
156 Should be a list of phandles to 143 Should be a list of phandles to CPU nodes (as described in
157 Documentation/devicetree/binding 144 Documentation/devicetree/bindings/arm/cpus.yaml).
158 145
159 required: 146 required:
160 - affinity 147 - affinity
161 148
162 clocks: <<
163 maxItems: 1 <<
164 <<
165 clock-names: <<
166 items: <<
167 - const: aclk <<
168 <<
169 power-domains: <<
170 maxItems: 1 <<
171 <<
172 resets: <<
173 maxItems: 1 <<
174 <<
175 mediatek,broken-save-restore-fw: <<
176 type: boolean <<
177 description: <<
178 Asserts that the firmware on this device <<
179 GICR registers when the GIC redistributo <<
180 <<
181 dependencies: 149 dependencies:
182 mbi-ranges: [ msi-controller ] 150 mbi-ranges: [ msi-controller ]
183 msi-controller: [ mbi-ranges ] 151 msi-controller: [ mbi-ranges ]
184 152
185 required: 153 required:
186 - compatible 154 - compatible
>> 155 - interrupts
187 - reg 156 - reg
188 157
189 patternProperties: 158 patternProperties:
190 "^gic-its@": false 159 "^gic-its@": false
191 "^interrupt-controller@[0-9a-f]+$": false 160 "^interrupt-controller@[0-9a-f]+$": false
192 # msi-controller is preferred, but allow oth 161 # msi-controller is preferred, but allow other names
193 "^(msi-controller|gic-its|interrupt-controll 162 "^(msi-controller|gic-its|interrupt-controller)@[0-9a-f]+$":
194 type: object 163 type: object
195 description: 164 description:
196 GICv3 has one or more Interrupt Translat 165 GICv3 has one or more Interrupt Translation Services (ITS) that are
197 used to route Message Signalled Interrup 166 used to route Message Signalled Interrupts (MSI) to the CPUs.
198 properties: 167 properties:
199 compatible: 168 compatible:
200 const: arm,gic-v3-its 169 const: arm,gic-v3-its
201 170
202 dma-noncoherent: <<
203 description: <<
204 Present if the GIC ITS permits progr <<
205 cacheability attributes but is conne <<
206 downstream interconnect. <<
207 <<
208 msi-controller: true 171 msi-controller: true
209 172
210 "#msi-cells": 173 "#msi-cells":
211 description: 174 description:
212 The single msi-cell is the DeviceID 175 The single msi-cell is the DeviceID of the device which will generate
213 the MSI. 176 the MSI.
214 const: 1 177 const: 1
215 178
216 reg: 179 reg:
217 description: 180 description:
218 Specifies the base physical address 181 Specifies the base physical address and size of the ITS registers.
219 maxItems: 1 182 maxItems: 1
220 183
221 socionext,synquacer-pre-its: 184 socionext,synquacer-pre-its:
222 description: 185 description:
223 (u32, u32) tuple describing the untr 186 (u32, u32) tuple describing the untranslated
224 address and size of the pre-ITS wind 187 address and size of the pre-ITS window.
225 $ref: /schemas/types.yaml#/definitions !! 188 allOf:
226 items: !! 189 - $ref: /schemas/types.yaml#/definitions/uint32-array
227 minItems: 2 !! 190 - items:
228 maxItems: 2 !! 191 minItems: 2
>> 192 maxItems: 2
229 193
230 required: 194 required:
231 - compatible 195 - compatible
232 - msi-controller 196 - msi-controller
233 - "#msi-cells" 197 - "#msi-cells"
234 - reg 198 - reg
235 199
236 additionalProperties: false 200 additionalProperties: false
237 201
238 additionalProperties: false 202 additionalProperties: false
239 203
240 examples: 204 examples:
241 - | 205 - |
242 gic: interrupt-controller@2cf00000 { 206 gic: interrupt-controller@2cf00000 {
243 compatible = "arm,gic-v3"; 207 compatible = "arm,gic-v3";
244 #interrupt-cells = <3>; 208 #interrupt-cells = <3>;
245 #address-cells = <1>; 209 #address-cells = <1>;
246 #size-cells = <1>; 210 #size-cells = <1>;
247 ranges; 211 ranges;
248 interrupt-controller; 212 interrupt-controller;
249 reg = <0x2f000000 0x10000>, // GICD 213 reg = <0x2f000000 0x10000>, // GICD
250 <0x2f100000 0x200000>, // GICR 214 <0x2f100000 0x200000>, // GICR
251 <0x2c000000 0x2000>, // GICC 215 <0x2c000000 0x2000>, // GICC
252 <0x2c010000 0x2000>, // GICH 216 <0x2c010000 0x2000>, // GICH
253 <0x2c020000 0x2000>; // GICV 217 <0x2c020000 0x2000>; // GICV
254 interrupts = <1 9 4>; 218 interrupts = <1 9 4>;
255 219
256 msi-controller; 220 msi-controller;
257 mbi-ranges = <256 128>; 221 mbi-ranges = <256 128>;
258 222
259 msi-controller@2c200000 { 223 msi-controller@2c200000 {
260 compatible = "arm,gic-v3-its"; 224 compatible = "arm,gic-v3-its";
261 msi-controller; 225 msi-controller;
262 #msi-cells = <1>; 226 #msi-cells = <1>;
263 reg = <0x2c200000 0x20000>; 227 reg = <0x2c200000 0x20000>;
264 }; 228 };
265 }; 229 };
266 230
267 - | <<
268 interrupt-controller@2c010000 { 231 interrupt-controller@2c010000 {
269 compatible = "arm,gic-v3"; 232 compatible = "arm,gic-v3";
270 #interrupt-cells = <4>; 233 #interrupt-cells = <4>;
271 #address-cells = <1>; 234 #address-cells = <1>;
272 #size-cells = <1>; 235 #size-cells = <1>;
273 ranges; 236 ranges;
274 interrupt-controller; 237 interrupt-controller;
275 redistributor-stride = <0x0 0x40000>; / 238 redistributor-stride = <0x0 0x40000>; // 256kB stride
276 #redistributor-regions = <2>; 239 #redistributor-regions = <2>;
277 reg = <0x2c010000 0x10000>, // GICD 240 reg = <0x2c010000 0x10000>, // GICD
278 <0x2d000000 0x800000>, // GICR 1: 241 <0x2d000000 0x800000>, // GICR 1: CPUs 0-31
279 <0x2e000000 0x800000>, // GICR 2: 242 <0x2e000000 0x800000>, // GICR 2: CPUs 32-63
280 <0x2c040000 0x2000>, // GICC 243 <0x2c040000 0x2000>, // GICC
281 <0x2c060000 0x2000>, // GICH 244 <0x2c060000 0x2000>, // GICH
282 <0x2c080000 0x2000>; // GICV 245 <0x2c080000 0x2000>; // GICV
283 interrupts = <1 9 4 0>; !! 246 interrupts = <1 9 4>;
284 247
285 msi-controller@2c200000 { 248 msi-controller@2c200000 {
286 compatible = "arm,gic-v3-its"; 249 compatible = "arm,gic-v3-its";
287 msi-controller; 250 msi-controller;
288 #msi-cells = <1>; 251 #msi-cells = <1>;
289 reg = <0x2c200000 0x20000>; 252 reg = <0x2c200000 0x20000>;
290 }; 253 };
291 254
292 msi-controller@2c400000 { 255 msi-controller@2c400000 {
293 compatible = "arm,gic-v3-its"; 256 compatible = "arm,gic-v3-its";
294 msi-controller; 257 msi-controller;
295 #msi-cells = <1>; 258 #msi-cells = <1>;
296 reg = <0x2c400000 0x20000>; 259 reg = <0x2c400000 0x20000>;
297 }; 260 };
298 261
299 ppi-partitions { 262 ppi-partitions {
300 part0: interrupt-partition-0 { 263 part0: interrupt-partition-0 {
301 affinity = <&cpu0>, <&cpu2>; !! 264 affinity = <&cpu0 &cpu2>;
302 }; 265 };
303 266
304 part1: interrupt-partition-1 { 267 part1: interrupt-partition-1 {
305 affinity = <&cpu1>, <&cpu3>; !! 268 affinity = <&cpu1 &cpu3>;
306 }; 269 };
307 }; 270 };
308 }; 271 };
309 272
310 273
311 device@0 { 274 device@0 {
312 reg = <0 4>; 275 reg = <0 4>;
313 interrupts = <1 1 4 &part0>; 276 interrupts = <1 1 4 &part0>;
314 }; 277 };
315 278
316 ... 279 ...
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