1 # SPDX-License-Identifier: GPL-2.0
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/interrupt-c
5 $schema: http://devicetree.org/meta-schemas/co
6
7 title: ARM Generic Interrupt Controller v1 and
8
9 maintainers:
10 - Marc Zyngier <marc.zyngier@arm.com>
11
12 description: |+
13 ARM SMP cores are often associated with a GI
14 interrupts (PPI), shared processor interrupt
15 generated interrupts (SGI).
16
17 Primary GIC is attached directly to the CPU
18 Secondary GICs are cascaded into the upward
19 have PPIs or SGIs.
20
21 allOf:
22 - $ref: /schemas/interrupt-controller.yaml#
23
24 properties:
25 compatible:
26 oneOf:
27 - items:
28 - enum:
29 - arm,arm11mp-gic
30 - arm,cortex-a15-gic
31 - arm,cortex-a7-gic
32 - arm,cortex-a5-gic
33 - arm,cortex-a9-gic
34 - arm,eb11mp-gic
35 - arm,gic-400
36 - arm,pl390
37 - arm,tc11mp-gic
38 - qcom,msm-8660-qgic
39 - qcom,msm-qgic2
40
41 - items:
42 - const: arm,gic-400
43 - enum:
44 - arm,cortex-a15-gic
45 - arm,cortex-a7-gic
46
47 - items:
48 - const: arm,arm1176jzf-devchip-gic
49 - const: arm,arm11mp-gic
50
51 - items:
52 - const: brcm,brahma-b15-gic
53 - const: arm,cortex-a15-gic
54
55 - oneOf:
56 - const: nvidia,tegra210-agic
57 - items:
58 - enum:
59 - nvidia,tegra186-agic
60 - nvidia,tegra194-agic
61 - nvidia,tegra234-agic
62 - const: nvidia,tegra210-agic
63
64 interrupt-controller: true
65
66 "#address-cells":
67 enum: [ 0, 1, 2 ]
68 "#size-cells":
69 enum: [ 1, 2 ]
70
71 "#interrupt-cells":
72 const: 3
73 description: |
74 The 1st cell is the interrupt type; 0 fo
75 interrupts.
76
77 The 2nd cell contains the interrupt numb
78 SPI interrupts are in the range [0-987].
79 range [0-15].
80
81 The 3rd cell is the flags, encoded as fo
82 bits[3:0] trigger type and level flags
83 1 = low-to-high edge triggered
84 2 = high-to-low edge triggered (inva
85 4 = active high level-sensitive
86 8 = active low level-sensitive (inva
87 bits[15:8] PPI interrupt cpu mask. Ea
88 the 8 possible cpus attached to the GI
89 the interrupt is wired to that CPU. O
90 Also note that the configurability of
91 DEFINED and as such not guaranteed to
92 in 2014 seem to ignore the setting of
93 default value).
94
95 reg:
96 description: |
97 Specifies base physical address(s) and s
98 first region is the GIC distributor regi
99 is the GIC cpu interface register base a
100
101 For GICv2 with virtualization extensions
102 required for specifying the base physica
103 registers. The first additional region i
104 control register base and size. The 2nd
105 virtual cpu interface register base and
106 minItems: 2
107 maxItems: 4
108
109 ranges: true
110
111 interrupts:
112 description: Interrupt source of the paren
113 secondary GICs, or VGIC maintenance inte
114 below).
115 maxItems: 1
116
117 cpu-offset:
118 description: per-cpu offset within the dis
119 regions, used when the GIC doesn't have
120 is cpu-offset * cpu-nr.
121 $ref: /schemas/types.yaml#/definitions/uin
122
123 clocks:
124 minItems: 1
125 maxItems: 2
126
127 clock-names:
128 description: List of names for the GIC clo
129 depend on the GIC variant.
130 oneOf:
131 - const: ic_clk # for "arm,arm11mp-gic"
132 - const: PERIPHCLKEN # for "arm,cortex-a
133 - items: # for "arm,cortex-a9-gic"
134 - const: PERIPHCLK
135 - const: PERIPHCLKEN
136 - const: clk # for "arm,gic-400" and "n
137 - const: gclk # for "arm,pl390"
138
139 power-domains:
140 maxItems: 1
141
142 resets:
143 maxItems: 1
144
145 required:
146 - compatible
147 - reg
148
149 patternProperties:
150 "^v2m@[0-9a-f]+$":
151 type: object
152 description: |
153 * GICv2m extension for MSI/MSI-x support
154
155 Certain revisions of GIC-400 supports MS
156 This is enabled by specifying v2m sub-no
157
158 properties:
159 compatible:
160 const: arm,gic-v2m-frame
161
162 msi-controller: true
163
164 reg:
165 maxItems: 1
166 description: GICv2m MSI interface regi
167
168 arm,msi-base-spi:
169 description: When the MSI_TYPER regist
170 this property should contain the SPI
171 the HW value.
172 $ref: /schemas/types.yaml#/definitions
173
174 arm,msi-num-spis:
175 description: When the MSI_TYPER regist
176 this property should contain the num
177 frame, overriding the HW value.
178 $ref: /schemas/types.yaml#/definitions
179
180 required:
181 - compatible
182 - msi-controller
183 - reg
184
185 additionalProperties: false
186
187 additionalProperties: false
188
189 examples:
190 - |
191 // GICv1
192 intc: interrupt-controller@fff11000 {
193 compatible = "arm,cortex-a9-gic";
194 #interrupt-cells = <3>;
195 #address-cells = <1>;
196 interrupt-controller;
197 reg = <0xfff11000 0x1000>,
198 <0xfff10100 0x100>;
199 };
200
201 - |
202 // GICv2
203 interrupt-controller@2c001000 {
204 compatible = "arm,cortex-a15-gic";
205 #interrupt-cells = <3>;
206 interrupt-controller;
207 reg = <0x2c001000 0x1000>,
208 <0x2c002000 0x2000>,
209 <0x2c004000 0x2000>,
210 <0x2c006000 0x2000>;
211 interrupts = <1 9 0xf04>;
212 };
213
214 - |
215 // GICv2m extension for MSI/MSI-x support
216 interrupt-controller@e1101000 {
217 compatible = "arm,gic-400";
218 #interrupt-cells = <3>;
219 #address-cells = <1>;
220 #size-cells = <1>;
221 interrupt-controller;
222 interrupts = <1 8 0xf04>;
223 ranges = <0 0xe1100000 0x100000>;
224 reg = <0xe1110000 0x01000>,
225 <0xe112f000 0x02000>,
226 <0xe1140000 0x10000>,
227 <0xe1160000 0x10000>;
228
229 v2m0: v2m@80000 {
230 compatible = "arm,gic-v2m-frame";
231 msi-controller;
232 reg = <0x80000 0x1000>;
233 };
234
235 //...
236
237 v2mN: v2m@90000 {
238 compatible = "arm,gic-v2m-frame";
239 msi-controller;
240 reg = <0x90000 0x1000>;
241 };
242 };
243 ...
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