1 This document describes the generic device tre
2 their master(s).
3
4 Message Signaled Interrupts (MSIs) are a class
5 write to an MMIO address.
6
7 MSIs were originally specified by PCI (and are
8 used with other busses, and hence a mechanism
9 those busses to the MSI controllers which they
10 potentially including additional information.
11
12 MSIs are distinguished by some combination of:
13
14 - The doorbell (the MMIO address written to).
15
16 Devices may be configured by software to wri
17 they can address. An MSI controller may feat
18
19 - The payload (the value written to the doorbe
20
21 Devices may be configured to write an arbitr
22 MSI controllers may have restrictions on per
23
24 - Sideband information accompanying the write.
25
26 Typically this is neither configurable nor p
27 taken through the memory system (i.e. it is
28 MSI controller and device rather than a prop
29
30
31 MSI controllers:
32 ================
33
34 An MSI controller signals interrupts to a CPU
35 address by some master. An MSI controller may
36
37 Required properties:
38 --------------------
39
40 - msi-controller: Identifies the node as an MS
41
42 Optional properties:
43 --------------------
44
45 - #msi-cells: The number of cells in an msi-sp
46
47 Typically this will encode information relat
48 not encode doorbells or payloads as these ca
49
50 The meaning of the msi-specifier is defined
51 the specific MSI controller.
52
53
54 MSI clients
55 ===========
56
57 MSI clients are devices which generate MSIs. F
58 generate, the doorbell and payload may be conf
59 information may not be configurable.
60
61 Required properties:
62 --------------------
63
64 - msi-parent: A list of phandle + msi-specifie
65 controller which the device is capable of us
66
67 This property is unordered, and MSIs may be
68 MSI controllers listed in the msi-parent pro
69
70 If a device has restrictions on the allocati
71 must be described with additional properties
72
73 When #msi-cells is non-zero, busses with an
74 additional properties to describe the relati
75 and the set of MSIs they can potentially gen
76
77
78 Example
79 =======
80
81 / {
82 #address-cells = <1>;
83 #size-cells = <1>;
84
85 msi_a: msi-controller@a {
86 reg = <0xa 0xf00>;
87 compatible = "vendor-a,some-co
88 msi-controller;
89 /* No sideband data, so #msi-c
90 };
91
92 msi_b: msi-controller@b {
93 reg = <0xb 0xf00>;
94 compatible = "vendor-b,another
95 msi-controller;
96 /* Each device has some unique
97 #msi-cells = <1>;
98 };
99
100 msi_c: msi-controller@c {
101 reg = <0xc 0xf00>;
102 compatible = "vendor-b,another
103 msi-controller;
104 /* Each device has some unique
105 #msi-cells = <1>;
106 };
107
108 dev@0 {
109 reg = <0x0 0xf00>;
110 compatible = "vendor-c,some-de
111
112 /* Can only generate MSIs to m
113 msi-parent = <&msi_a>;
114 };
115
116 dev@1 {
117 reg = <0x1 0xf00>;
118 compatible = "vendor-c,some-de
119
120 /*
121 * Can generate MSIs to either
122 */
123 msi-parent = <&msi_a>, <&msi_b
124 };
125
126 dev@2 {
127 reg = <0x2 0xf00>;
128 compatible = "vendor-c,some-de
129 /*
130 * Has different IDs at each M
131 * Can generate MSIs to all of
132 */
133 msi-parent = <&msi_a>, <&msi_b
134 };
135 };
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