1 * Open PIC Binding 1 * Open PIC Binding
2 2
3 This binding specifies what properties must be 3 This binding specifies what properties must be available in the device tree
4 representation of an Open PIC compliant interr 4 representation of an Open PIC compliant interrupt controller. This binding is
5 based on the binding defined for Open PIC in [ 5 based on the binding defined for Open PIC in [1] and is a superset of that
6 binding. 6 binding.
7 7
8 Required properties: 8 Required properties:
9 9
10 NOTE: Many of these descriptions were paraph 10 NOTE: Many of these descriptions were paraphrased here from [1] to aid
11 readability. 11 readability.
12 12
13 - compatible: Specifies the compatibility 13 - compatible: Specifies the compatibility list for the PIC. The type
14 shall be <string> and the value shall in 14 shall be <string> and the value shall include "open-pic".
15 15
16 - reg: Specifies the base physical address 16 - reg: Specifies the base physical address(s) and size(s) of this
17 PIC's addressable register space. The t 17 PIC's addressable register space. The type shall be <prop-encoded-array>.
18 18
19 - interrupt-controller: The presence of th 19 - interrupt-controller: The presence of this property identifies the node
20 as an Open PIC. No property value shall 20 as an Open PIC. No property value shall be defined.
21 21
22 - #interrupt-cells: Specifies the number o 22 - #interrupt-cells: Specifies the number of cells needed to encode an
23 interrupt source. The type shall be a < 23 interrupt source. The type shall be a <u32> and the value shall be 2.
24 24
25 - #address-cells: Specifies the number of 25 - #address-cells: Specifies the number of cells needed to encode an
26 address. The type shall be <u32> and th 26 address. The type shall be <u32> and the value shall be 0. As such,
27 'interrupt-map' nodes do not have to spe 27 'interrupt-map' nodes do not have to specify a parent unit address.
28 28
29 Optional properties: 29 Optional properties:
30 30
31 - pic-no-reset: The presence of this prope 31 - pic-no-reset: The presence of this property indicates that the PIC
32 shall not be reset during runtime initia 32 shall not be reset during runtime initialization. No property value shall
33 be defined. The presence of this proper 33 be defined. The presence of this property also mandates that any
34 initialization related to interrupt sour 34 initialization related to interrupt sources shall be limited to sources
35 explicitly referenced in the device tree 35 explicitly referenced in the device tree.
36 36
37 * Interrupt Specifier Definition 37 * Interrupt Specifier Definition
38 38
39 Interrupt specifiers consists of 2 cells enc 39 Interrupt specifiers consists of 2 cells encoded as
40 follows: 40 follows:
41 41
42 - <1st-cell>: The interrupt-number that id 42 - <1st-cell>: The interrupt-number that identifies the interrupt source.
43 43
44 - <2nd-cell>: The level-sense information, 44 - <2nd-cell>: The level-sense information, encoded as follows:
45 0 = low-to-high edge trigg 45 0 = low-to-high edge triggered
46 1 = active low level-sensi 46 1 = active low level-sensitive
47 2 = active high level-sens 47 2 = active high level-sensitive
48 3 = high-to-low edge trigg 48 3 = high-to-low edge triggered
49 49
50 * Examples 50 * Examples
51 51
52 Example 1: 52 Example 1:
53 53
54 /* 54 /*
55 * An Open PIC interrupt controller 55 * An Open PIC interrupt controller
56 */ 56 */
57 mpic: pic@40000 { 57 mpic: pic@40000 {
58 // This is an interrupt contro 58 // This is an interrupt controller node.
59 interrupt-controller; 59 interrupt-controller;
60 60
61 // No address cells so that 'i 61 // No address cells so that 'interrupt-map' nodes which reference
62 // this Open PIC node do not n 62 // this Open PIC node do not need a parent address specifier.
63 #address-cells = <0>; 63 #address-cells = <0>;
64 64
65 // Two cells to encode interru 65 // Two cells to encode interrupt sources.
66 #interrupt-cells = <2>; 66 #interrupt-cells = <2>;
67 67
68 // Offset address of 0x40000 a 68 // Offset address of 0x40000 and size of 0x40000.
69 reg = <0x40000 0x40000>; 69 reg = <0x40000 0x40000>;
70 70
71 // Compatible with Open PIC. 71 // Compatible with Open PIC.
72 compatible = "open-pic"; 72 compatible = "open-pic";
73 73
74 // The PIC shall not be reset. 74 // The PIC shall not be reset.
75 pic-no-reset; 75 pic-no-reset;
76 }; 76 };
77 77
78 Example 2: 78 Example 2:
79 79
80 /* 80 /*
81 * An interrupt generating device that 81 * An interrupt generating device that is wired to an Open PIC.
82 */ 82 */
83 serial0: serial@4500 { 83 serial0: serial@4500 {
84 // Interrupt source '42' that 84 // Interrupt source '42' that is active high level-sensitive.
85 // Note that there are only tw 85 // Note that there are only two cells as specified in the interrupt
86 // parent's '#interrupt-cells' 86 // parent's '#interrupt-cells' property.
87 interrupts = <42 2>; 87 interrupts = <42 2>;
88 88
89 // The interrupt controller th 89 // The interrupt controller that this device is wired to.
90 interrupt-parent = <&mpic>; 90 interrupt-parent = <&mpic>;
91 }; 91 };
92 92
93 * References 93 * References
94 94
95 [1] Devicetree Specification 95 [1] Devicetree Specification
96 (https://www.devicetree.org/specifications 96 (https://www.devicetree.org/specifications/)
97 97
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.