1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/interrupt-c 4 $id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Renesas RZ/G2L (and alike SoC's) Interr 7 title: Renesas RZ/G2L (and alike SoC's) Interrupt Controller (IA55)
8 8
9 maintainers: 9 maintainers:
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp. 10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be 11 - Geert Uytterhoeven <geert+renesas@glider.be>
12 12
13 description: | 13 description: |
14 IA55 performs various interrupt controls inc 14 IA55 performs various interrupt controls including synchronization for the external
15 interrupts of NMI, IRQ, and GPIOINT and the 15 interrupts of NMI, IRQ, and GPIOINT and the interrupts of the built-in peripheral
16 interrupts output by each IP. And it notifie 16 interrupts output by each IP. And it notifies the interrupt to the GIC
17 - IRQ sense select for 8 external interrup 17 - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts
18 - GPIO pins used as external interrupt inp 18 - GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts
19 - NMI edge select (NMI is not treated as N 19 - NMI edge select (NMI is not treated as NMI exception and supports fall edge and
20 stand-up edge detection interrupts) 20 stand-up edge detection interrupts)
21 21
22 properties: 22 properties:
23 compatible: 23 compatible:
24 oneOf: !! 24 items:
25 - items: !! 25 - enum:
26 - enum: !! 26 - renesas,r9a07g043u-irqc # RZ/G2UL
27 - renesas,r9a07g043u-irqc # R !! 27 - renesas,r9a07g044-irqc # RZ/G2{L,LC}
28 - renesas,r9a07g044-irqc # R !! 28 - renesas,r9a07g054-irqc # RZ/V2L
29 - renesas,r9a07g054-irqc # R !! 29 - renesas,r9a08g045-irqc # RZ/G3S
30 - renesas,r9a08g045-irqc # R !! 30 - const: renesas,rzg2l-irqc
31 - const: renesas,rzg2l-irqc <<
32 <<
33 - const: renesas,r9a07g043f-irqc # R <<
34 31
35 '#interrupt-cells': 32 '#interrupt-cells':
36 description: The first cell should contain 33 description: The first cell should contain a macro RZG2L_{NMI,IRQX} included in the
37 include/dt-bindings/interrupt 34 include/dt-bindings/interrupt-controller/irqc-rzg2l.h and the second
38 cell is used to specify the f 35 cell is used to specify the flag.
39 const: 2 36 const: 2
40 37
41 '#address-cells': 38 '#address-cells':
42 const: 0 39 const: 0
43 40
44 interrupt-controller: true 41 interrupt-controller: true
45 42
46 reg: 43 reg:
47 maxItems: 1 44 maxItems: 1
48 45
49 interrupts: 46 interrupts:
50 minItems: 45 !! 47 minItems: 41
51 items: 48 items:
52 - description: NMI interrupt 49 - description: NMI interrupt
53 - description: IRQ0 interrupt 50 - description: IRQ0 interrupt
54 - description: IRQ1 interrupt 51 - description: IRQ1 interrupt
55 - description: IRQ2 interrupt 52 - description: IRQ2 interrupt
56 - description: IRQ3 interrupt 53 - description: IRQ3 interrupt
57 - description: IRQ4 interrupt 54 - description: IRQ4 interrupt
58 - description: IRQ5 interrupt 55 - description: IRQ5 interrupt
59 - description: IRQ6 interrupt 56 - description: IRQ6 interrupt
60 - description: IRQ7 interrupt 57 - description: IRQ7 interrupt
61 - description: GPIO interrupt, TINT0 58 - description: GPIO interrupt, TINT0
62 - description: GPIO interrupt, TINT1 59 - description: GPIO interrupt, TINT1
63 - description: GPIO interrupt, TINT2 60 - description: GPIO interrupt, TINT2
64 - description: GPIO interrupt, TINT3 61 - description: GPIO interrupt, TINT3
65 - description: GPIO interrupt, TINT4 62 - description: GPIO interrupt, TINT4
66 - description: GPIO interrupt, TINT5 63 - description: GPIO interrupt, TINT5
67 - description: GPIO interrupt, TINT6 64 - description: GPIO interrupt, TINT6
68 - description: GPIO interrupt, TINT7 65 - description: GPIO interrupt, TINT7
69 - description: GPIO interrupt, TINT8 66 - description: GPIO interrupt, TINT8
70 - description: GPIO interrupt, TINT9 67 - description: GPIO interrupt, TINT9
71 - description: GPIO interrupt, TINT10 68 - description: GPIO interrupt, TINT10
72 - description: GPIO interrupt, TINT11 69 - description: GPIO interrupt, TINT11
73 - description: GPIO interrupt, TINT12 70 - description: GPIO interrupt, TINT12
74 - description: GPIO interrupt, TINT13 71 - description: GPIO interrupt, TINT13
75 - description: GPIO interrupt, TINT14 72 - description: GPIO interrupt, TINT14
76 - description: GPIO interrupt, TINT15 73 - description: GPIO interrupt, TINT15
77 - description: GPIO interrupt, TINT16 74 - description: GPIO interrupt, TINT16
78 - description: GPIO interrupt, TINT17 75 - description: GPIO interrupt, TINT17
79 - description: GPIO interrupt, TINT18 76 - description: GPIO interrupt, TINT18
80 - description: GPIO interrupt, TINT19 77 - description: GPIO interrupt, TINT19
81 - description: GPIO interrupt, TINT20 78 - description: GPIO interrupt, TINT20
82 - description: GPIO interrupt, TINT21 79 - description: GPIO interrupt, TINT21
83 - description: GPIO interrupt, TINT22 80 - description: GPIO interrupt, TINT22
84 - description: GPIO interrupt, TINT23 81 - description: GPIO interrupt, TINT23
85 - description: GPIO interrupt, TINT24 82 - description: GPIO interrupt, TINT24
86 - description: GPIO interrupt, TINT25 83 - description: GPIO interrupt, TINT25
87 - description: GPIO interrupt, TINT26 84 - description: GPIO interrupt, TINT26
88 - description: GPIO interrupt, TINT27 85 - description: GPIO interrupt, TINT27
89 - description: GPIO interrupt, TINT28 86 - description: GPIO interrupt, TINT28
90 - description: GPIO interrupt, TINT29 87 - description: GPIO interrupt, TINT29
91 - description: GPIO interrupt, TINT30 88 - description: GPIO interrupt, TINT30
92 - description: GPIO interrupt, TINT31 89 - description: GPIO interrupt, TINT31
93 - description: Bus error interrupt 90 - description: Bus error interrupt
94 - description: ECCRAM0 or combined ECCRA <<
95 - description: ECCRAM0 or combined ECCRA <<
96 - description: ECCRAM0 or combined ECCRA <<
97 - description: ECCRAM1 1bit error interr <<
98 - description: ECCRAM1 2bit error interr <<
99 - description: ECCRAM1 error overflow in <<
100 91
101 interrupt-names: 92 interrupt-names:
102 minItems: 45 !! 93 minItems: 41
103 items: 94 items:
104 - const: nmi 95 - const: nmi
105 - const: irq0 96 - const: irq0
106 - const: irq1 97 - const: irq1
107 - const: irq2 98 - const: irq2
108 - const: irq3 99 - const: irq3
109 - const: irq4 100 - const: irq4
110 - const: irq5 101 - const: irq5
111 - const: irq6 102 - const: irq6
112 - const: irq7 103 - const: irq7
113 - const: tint0 104 - const: tint0
114 - const: tint1 105 - const: tint1
115 - const: tint2 106 - const: tint2
116 - const: tint3 107 - const: tint3
117 - const: tint4 108 - const: tint4
118 - const: tint5 109 - const: tint5
119 - const: tint6 110 - const: tint6
120 - const: tint7 111 - const: tint7
121 - const: tint8 112 - const: tint8
122 - const: tint9 113 - const: tint9
123 - const: tint10 114 - const: tint10
124 - const: tint11 115 - const: tint11
125 - const: tint12 116 - const: tint12
126 - const: tint13 117 - const: tint13
127 - const: tint14 118 - const: tint14
128 - const: tint15 119 - const: tint15
129 - const: tint16 120 - const: tint16
130 - const: tint17 121 - const: tint17
131 - const: tint18 122 - const: tint18
132 - const: tint19 123 - const: tint19
133 - const: tint20 124 - const: tint20
134 - const: tint21 125 - const: tint21
135 - const: tint22 126 - const: tint22
136 - const: tint23 127 - const: tint23
137 - const: tint24 128 - const: tint24
138 - const: tint25 129 - const: tint25
139 - const: tint26 130 - const: tint26
140 - const: tint27 131 - const: tint27
141 - const: tint28 132 - const: tint28
142 - const: tint29 133 - const: tint29
143 - const: tint30 134 - const: tint30
144 - const: tint31 135 - const: tint31
145 - const: bus-err 136 - const: bus-err
146 - const: ec7tie1-0 <<
147 - const: ec7tie2-0 <<
148 - const: ec7tiovf-0 <<
149 - const: ec7tie1-1 <<
150 - const: ec7tie2-1 <<
151 - const: ec7tiovf-1 <<
152 137
153 clocks: 138 clocks:
154 maxItems: 2 139 maxItems: 2
155 140
156 clock-names: 141 clock-names:
157 items: 142 items:
158 - const: clk 143 - const: clk
159 - const: pclk 144 - const: pclk
160 145
161 power-domains: 146 power-domains:
162 maxItems: 1 147 maxItems: 1
163 148
164 resets: 149 resets:
165 maxItems: 1 150 maxItems: 1
166 151
167 required: 152 required:
168 - compatible 153 - compatible
169 - '#interrupt-cells' 154 - '#interrupt-cells'
170 - '#address-cells' 155 - '#address-cells'
171 - interrupt-controller 156 - interrupt-controller
172 - reg 157 - reg
173 - interrupts 158 - interrupts
174 - interrupt-names <<
175 - clocks 159 - clocks
176 - clock-names 160 - clock-names
177 - power-domains 161 - power-domains
178 - resets 162 - resets
179 163
180 allOf: 164 allOf:
181 - $ref: /schemas/interrupt-controller.yaml# 165 - $ref: /schemas/interrupt-controller.yaml#
182 166
183 - if: 167 - if:
184 properties: 168 properties:
185 compatible: 169 compatible:
186 contains: 170 contains:
187 enum: 171 enum:
>> 172 - renesas,r9a07g043u-irqc
188 - renesas,r9a08g045-irqc 173 - renesas,r9a08g045-irqc
189 then: 174 then:
190 properties: 175 properties:
191 interrupts: 176 interrupts:
192 maxItems: 45 !! 177 minItems: 42
193 interrupt-names: <<
194 maxItems: 45 <<
195 else: <<
196 properties: <<
197 interrupts: <<
198 minItems: 48 <<
199 interrupt-names: 178 interrupt-names:
200 minItems: 48 !! 179 minItems: 42
>> 180 required:
>> 181 - interrupt-names
201 182
202 unevaluatedProperties: false 183 unevaluatedProperties: false
203 184
204 examples: 185 examples:
205 - | 186 - |
206 #include <dt-bindings/interrupt-controller 187 #include <dt-bindings/interrupt-controller/arm-gic.h>
207 #include <dt-bindings/clock/r9a07g044-cpg. 188 #include <dt-bindings/clock/r9a07g044-cpg.h>
208 189
209 irqc: interrupt-controller@110a0000 { 190 irqc: interrupt-controller@110a0000 {
210 compatible = "renesas,r9a07g044-irqc", 191 compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc";
211 reg = <0x110a0000 0x10000>; 192 reg = <0x110a0000 0x10000>;
212 #interrupt-cells = <2>; 193 #interrupt-cells = <2>;
213 #address-cells = <0>; 194 #address-cells = <0>;
214 interrupt-controller; 195 interrupt-controller;
215 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL 196 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 1 IRQ_TYPE_LEVEL 197 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 2 IRQ_TYPE_LEVEL 198 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 3 IRQ_TYPE_LEVEL 199 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 4 IRQ_TYPE_LEVEL 200 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 5 IRQ_TYPE_LEVEL 201 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 6 IRQ_TYPE_LEVEL 202 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 7 IRQ_TYPE_LEVEL 203 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 8 IRQ_TYPE_LEVEL 204 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
224 <GIC_SPI 444 IRQ_TYPE_LEV 205 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
225 <GIC_SPI 445 IRQ_TYPE_LEV 206 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 446 IRQ_TYPE_LEV 207 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 447 IRQ_TYPE_LEV 208 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 448 IRQ_TYPE_LEV 209 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
229 <GIC_SPI 449 IRQ_TYPE_LEV 210 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
230 <GIC_SPI 450 IRQ_TYPE_LEV 211 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
231 <GIC_SPI 451 IRQ_TYPE_LEV 212 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 452 IRQ_TYPE_LEV 213 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
233 <GIC_SPI 453 IRQ_TYPE_LEV 214 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 454 IRQ_TYPE_LEV 215 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
235 <GIC_SPI 455 IRQ_TYPE_LEV 216 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
236 <GIC_SPI 456 IRQ_TYPE_LEV 217 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 457 IRQ_TYPE_LEV 218 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 458 IRQ_TYPE_LEV 219 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 459 IRQ_TYPE_LEV 220 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 460 IRQ_TYPE_LEV 221 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 461 IRQ_TYPE_LEV 222 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
242 <GIC_SPI 462 IRQ_TYPE_LEV 223 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
243 <GIC_SPI 463 IRQ_TYPE_LEV 224 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
244 <GIC_SPI 464 IRQ_TYPE_LEV 225 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
245 <GIC_SPI 465 IRQ_TYPE_LEV 226 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
246 <GIC_SPI 466 IRQ_TYPE_LEV 227 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 467 IRQ_TYPE_LEV 228 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
248 <GIC_SPI 468 IRQ_TYPE_LEV 229 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
249 <GIC_SPI 469 IRQ_TYPE_LEV 230 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 470 IRQ_TYPE_LEV 231 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 471 IRQ_TYPE_LEV 232 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 472 IRQ_TYPE_LEV 233 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 473 IRQ_TYPE_LEV 234 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 474 IRQ_TYPE_LEV 235 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 475 IRQ_TYPE_LEV !! 236 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
256 <GIC_SPI 25 IRQ_TYPE_EDGE <<
257 <GIC_SPI 34 IRQ_TYPE_EDGE <<
258 <GIC_SPI 35 IRQ_TYPE_EDGE <<
259 <GIC_SPI 36 IRQ_TYPE_EDGE <<
260 <GIC_SPI 37 IRQ_TYPE_EDGE <<
261 <GIC_SPI 38 IRQ_TYPE_EDGE <<
262 <GIC_SPI 39 IRQ_TYPE_EDGE <<
263 interrupt-names = "nmi", 237 interrupt-names = "nmi",
264 "irq0", "irq1", "irq 238 "irq0", "irq1", "irq2", "irq3",
265 "irq4", "irq5", "irq 239 "irq4", "irq5", "irq6", "irq7",
266 "tint0", "tint1", "t 240 "tint0", "tint1", "tint2", "tint3",
267 "tint4", "tint5", "t 241 "tint4", "tint5", "tint6", "tint7",
268 "tint8", "tint9", "t 242 "tint8", "tint9", "tint10", "tint11",
269 "tint12", "tint13", 243 "tint12", "tint13", "tint14", "tint15",
270 "tint16", "tint17", 244 "tint16", "tint17", "tint18", "tint19",
271 "tint20", "tint21", 245 "tint20", "tint21", "tint22", "tint23",
272 "tint24", "tint25", 246 "tint24", "tint25", "tint26", "tint27",
273 "tint28", "tint29", !! 247 "tint28", "tint29", "tint30", "tint31";
274 "bus-err", "ec7tie1- <<
275 "ec7tiovf-0", "ec7ti <<
276 "ec7tiovf-1"; <<
277 clocks = <&cpg CPG_MOD R9A07G044_IA55_ 248 clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
278 <&cpg CPG_MOD R9A07G044_IA55_ 249 <&cpg CPG_MOD R9A07G044_IA55_PCLK>;
279 clock-names = "clk", "pclk"; 250 clock-names = "clk", "pclk";
280 power-domains = <&cpg>; 251 power-domains = <&cpg>;
281 resets = <&cpg R9A07G044_IA55_RESETN>; 252 resets = <&cpg R9A07G044_IA55_RESETN>;
282 }; 253 };
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