1 * SPEAr Shared IRQ layer (shirq)
2
3 SPEAr3xx architecture includes shared/multiple
4 of devices. The multiplexor provides a single
5 interrupt controller (VIC) on behalf of a grou
6
7 There can be multiple groups available on SPEA
8 exceeding 4. The number of devices in a group
9 may share same set of status/mask registers sp
10 bit masks. Also in some cases the group may no
11 registers. This makes software little complex.
12
13 A single node in the device tree is used to de
14 interrupt multiplexor (one node for all groups
15 interrupt controller shares config/control reg
16 For example, a 32-bit interrupt enable/disable
17 accommodate up to 4 interrupt groups.
18
19 Required properties:
20 - compatible: should be, either of
21 - "st,spear300-shirq"
22 - "st,spear310-shirq"
23 - "st,spear320-shirq"
24 - interrupt-controller: Identifies the node
25 - #interrupt-cells: should be <1> which basi
26 (starting from 0) of interrupts for all th
27 - reg: Base address and size of shirq regist
28 - interrupts: The list of interrupts generat
29 then connected to a parent interrupt contr
30 associated with one of the interrupts, hen
31 parent) is equal to number of groups. The
32 specifier depends in the interrupt parent
33
34 Example:
35
36 The following is an example from the SPEAr320
37
38 shirq: interrupt-controller@b3000000 {
39 compatible = "st,spear320-shirq";
40 reg = <0xb3000000 0x1000>;
41 interrupts = <28 29 30 1>;
42 #interrupt-cells = <1>;
43 interrupt-controller;
44 };
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