1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/interrupt-c 4 $id: http://devicetree.org/schemas/interrupt-controller/st,stih407-irq-syscfg.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: STMicroelectronics STi System Configura 7 title: STMicroelectronics STi System Configuration Controlled IRQs
8 8
9 maintainers: 9 maintainers:
10 - Patrice Chotard <patrice.chotard@foss.st.co 10 - Patrice Chotard <patrice.chotard@foss.st.com>
11 11
12 description: 12 description:
13 On STi based systems; External, CTI (Core Si 13 On STi based systems; External, CTI (Core Sight), PMU (Performance
14 Management), and PL310 L2 Cache IRQs are con 14 Management), and PL310 L2 Cache IRQs are controlled using System
15 Configuration registers. This device is use 15 Configuration registers. This device is used to unmask them prior to use.
16 16
17 properties: 17 properties:
18 compatible: 18 compatible:
19 const: st,stih407-irq-syscfg 19 const: st,stih407-irq-syscfg
20 20
21 st,syscfg: 21 st,syscfg:
22 description: Phandle to Cortex-A9 IRQ syst 22 description: Phandle to Cortex-A9 IRQ system config registers
23 $ref: /schemas/types.yaml#/definitions/pha 23 $ref: /schemas/types.yaml#/definitions/phandle
24 24
25 st,irq-device: 25 st,irq-device:
26 description: Array of IRQs to enable. 26 description: Array of IRQs to enable.
27 $ref: /schemas/types.yaml#/definitions/uin 27 $ref: /schemas/types.yaml#/definitions/uint32-array
28 items: 28 items:
29 - description: Enable the IRQ of the cha 29 - description: Enable the IRQ of the channel one.
30 - description: Enable the IRQ of the cha 30 - description: Enable the IRQ of the channel two.
31 31
32 st,fiq-device: 32 st,fiq-device:
33 description: Array of FIQs to enable. 33 description: Array of FIQs to enable.
34 $ref: /schemas/types.yaml#/definitions/uin 34 $ref: /schemas/types.yaml#/definitions/uint32-array
35 items: 35 items:
36 - description: Enable the IRQ of the cha 36 - description: Enable the IRQ of the channel one.
37 - description: Enable the IRQ of the cha 37 - description: Enable the IRQ of the channel two.
38 38
39 st,invert-ext: 39 st,invert-ext:
40 description: External IRQs can be inverted 40 description: External IRQs can be inverted at will. This property inverts
41 these three IRQs using bitwise logic, ea 41 these three IRQs using bitwise logic, each one being encoded respectively
42 on the first, second and fourth bit. 42 on the first, second and fourth bit.
43 $ref: /schemas/types.yaml#/definitions/uin 43 $ref: /schemas/types.yaml#/definitions/uint32
44 enum: [ 1, 2, 3, 4, 5, 6 ] 44 enum: [ 1, 2, 3, 4, 5, 6 ]
45 45
46 required: 46 required:
47 - compatible 47 - compatible
48 - st,syscfg 48 - st,syscfg
49 - st,irq-device 49 - st,irq-device
50 - st,fiq-device 50 - st,fiq-device
51 51
52 additionalProperties: false 52 additionalProperties: false
53 53
54 examples: 54 examples:
55 - | 55 - |
56 #include <dt-bindings/interrupt-controller 56 #include <dt-bindings/interrupt-controller/irq-st.h>
57 irq-syscfg { 57 irq-syscfg {
58 compatible = "st,stih407-irq-syscfg"; 58 compatible = "st,stih407-irq-syscfg";
59 st,syscfg = <&syscfg_cpu>; 59 st,syscfg = <&syscfg_cpu>;
60 st,irq-device = <ST_IRQ_SYSCFG_PMU_0>, 60 st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
61 <ST_IRQ_SYSCFG_PMU_1>; 61 <ST_IRQ_SYSCFG_PMU_1>;
62 st,fiq-device = <ST_IRQ_SYSCFG_DISABLE 62 st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
63 <ST_IRQ_SYSCFG_DISABLE 63 <ST_IRQ_SYSCFG_DISABLED>;
64 }; 64 };
65 ... 65 ...
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